From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A71F0C4167B for ; Sat, 17 Dec 2022 18:05:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbiLQSFQ (ORCPT ); Sat, 17 Dec 2022 13:05:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229453AbiLQSFO (ORCPT ); Sat, 17 Dec 2022 13:05:14 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E97713EB7; Sat, 17 Dec 2022 10:05:13 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CBCDEB802C3; Sat, 17 Dec 2022 18:05:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57F22C433D2; Sat, 17 Dec 2022 18:05:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1671300310; bh=/Uc2Dbixn2Du0U4OtE/VQPRi6FRx3WQWkyH/6XtWzdE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Zc1r4lZW2vM7FxQea2mBSHn/RGUd/wpUjnwkwYmZtoPgVDQdLZPu+3PRHbuEjyiiY /AW1QM9pF1ImEfgZxuXr+YKALiVtOUVU1Gsi8fCiz+nyOiy3ihGM8tBIc1ek+Ytsny SvXFrdj8wJC65n3stRkvEOFYSUP3x/0VyJA1oNNpKDxpWF2arWZHDa8Pb4piU60UYB 3RDRtplo+T0CmVmnxZA1C5WID0aHyKH7aPqgOWo488y7NFo1SFAR52qyPn2ztYszOf 7foJ8CI3Mj3upw+fXdGgD5cOXE2nsUUnf19w2qby7d6UuJJnv1ZD+n/ay+dLY05//b 53xUILcwzsuGg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p6bYa-00DJod-1O; Sat, 17 Dec 2022 18:05:08 +0000 Date: Sat, 17 Dec 2022 18:05:07 +0000 Message-ID: <86r0wxq52k.wl-maz@kernel.org> From: Marc Zyngier To: Sasha Levin Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Jianmin Lv , Huacai Chen , bhelgaas@google.com, rafael@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org Subject: Re: [PATCH AUTOSEL 5.4 7/9] ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity In-Reply-To: <20221217152949.99146-7-sashal@kernel.org> References: <20221217152949.99146-1-sashal@kernel.org> <20221217152949.99146-7-sashal@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashal@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, lvjianmin@loongson.cn, chenhuacai@loongson.cn, bhelgaas@google.com, rafael@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Sat, 17 Dec 2022 15:29:45 +0000, Sasha Levin wrote: > > From: Jianmin Lv > > [ Upstream commit d0c50cc4b957b2cf6e43cec4998d212b5abe9220 ] > > On LoongArch based systems, the PCI devices (e.g. SATA controllers and > PCI-to-PCI bridge controllers) in Loongson chipsets output high-level > interrupt signal to the interrupt controller they are connected (see > Loongson 7A1000 Bridge User Manual v2.00, sec 5.3, "For the bridge chip, > AC97 DMA interrupts are edge triggered, gpio interrupts can be configured > to be level triggered or edge triggered as needed, and the rest of the > interrupts are level triggered and active high."), while the IRQs are > active low from the perspective of PCI (see Conventional PCI spec r3.0, > sec 2.2.6, "Interrupts on PCI are optional and defined as level sensitive, > asserted low."), which means that the interrupt output of PCI devices plugged > into PCI-to-PCI bridges of Loongson chipset will be also converted to high-level. > So high level triggered type is required to be passed to acpi_register_gsi() > when creating mappings for PCI devices. > > Signed-off-by: Jianmin Lv > Reviewed-by: Huacai Chen > Signed-off-by: Marc Zyngier > Link: https://lore.kernel.org/r/20221022075955.11726-2-lvjianmin@loongson.cn > Signed-off-by: Sasha Levin > --- > drivers/acpi/pci_irq.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c > index dea8a60e18a4..7b843a70f33d 100644 > --- a/drivers/acpi/pci_irq.c > +++ b/drivers/acpi/pci_irq.c > @@ -399,13 +399,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev) > u8 pin; > int triggering = ACPI_LEVEL_SENSITIVE; > /* > - * On ARM systems with the GIC interrupt model, level interrupts > + * On ARM systems with the GIC interrupt model, or LoongArch > + * systems with the LPIC interrupt model, level interrupts > * are always polarity high by specification; PCI legacy > * IRQs lines are inverted before reaching the interrupt > * controller and must therefore be considered active high > * as default. > */ > - int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ? > + int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC || > + acpi_irq_model == ACPI_IRQ_MODEL_LPIC ? > ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW; > char *link = NULL; > char link_desc[16]; This cannot even compile, as the *architecture* is not even supported in 5.4. Please drop this patch. M. -- Without deviation from the norm, progress is not possible.