[PATCH] mailbox: pcc: don't zero error register

[PATCH] mailbox: pcc: don't zero error register

[Punit Agrawal]

From: Jamie Iles <jamie.iles@oss.qualcomm.com>

The error status mask for a type 3/4 subspace is used for reading the
error status, and the bitwise inverse is used for clearing the error
with the intent being to preserve any of the non-error bits.  However,
we were previously applying the mask to extract the status and then
applying the inverse to the result which ended up clearing all bits.

Instead, store the inverse mask in the preserve mask and then use that
on the original value read from the error status so that only the error
is cleared.

Fixes: c45ded7e1135 ("mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)")
Signed-off-by: Jamie Iles <jamie.iles@oss.qualcomm.com>
Signed-off-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com>
---
 drivers/mailbox/pcc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c
index 1aa3a7dbb7be..5b454769d260 100644
--- a/drivers/mailbox/pcc.c
+++ b/drivers/mailbox/pcc.c
@@ -281,9 +281,8 @@ static int pcc_mbox_error_check_and_clear(struct pcc_chan_info *pchan)
 	if (ret)
 		return ret;
 
-	val &= pchan->error.status_mask;
-	if (val) {
-		val &= ~pchan->error.status_mask;
+	if (val & pchan->error.status_mask) {
+		val &= pchan->error.preserve_mask;
 		pcc_chan_reg_write(&pchan->error, val);
 		return -EIO;
 	}
@@ -750,7 +749,8 @@ static int pcc_parse_subspace_db_reg(struct pcc_chan_info *pchan,
 
 		ret = pcc_chan_reg_init(&pchan->error,
 					&pcct_ext->error_status_register,
-					0, 0, pcct_ext->error_status_mask,
+					~pcct_ext->error_status_mask, 0,
+					pcct_ext->error_status_mask,
 					"Error Status");
 	}
 	return ret;
-- 
2.34.1

Re: [PATCH] mailbox: pcc: don't zero error register

[Sudeep Holla]

On Wed, Nov 05, 2025 at 02:42:29PM +0000, Punit Agrawal wrote:
> From: Jamie Iles <jamie.iles@oss.qualcomm.com>
> 
> The error status mask for a type 3/4 subspace is used for reading the
> error status, and the bitwise inverse is used for clearing the error
> with the intent being to preserve any of the non-error bits.  However,
> we were previously applying the mask to extract the status and then
> applying the inverse to the result which ended up clearing all bits.
> 
> Instead, store the inverse mask in the preserve mask and then use that
> on the original value read from the error status so that only the error
> is cleared.
> 
> Fixes: c45ded7e1135 ("mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)")

Good catch!

Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

-- 
Regards,
Sudeep

Re: [PATCH] mailbox: pcc: don't zero error register

[Punit Agrawal]

Sudeep Holla <sudeep.holla@arm.com> writes:

> On Wed, Nov 05, 2025 at 02:42:29PM +0000, Punit Agrawal wrote:
>> From: Jamie Iles <jamie.iles@oss.qualcomm.com>
>> 
>> The error status mask for a type 3/4 subspace is used for reading the
>> error status, and the bitwise inverse is used for clearing the error
>> with the intent being to preserve any of the non-error bits.  However,
>> we were previously applying the mask to extract the status and then
>> applying the inverse to the result which ended up clearing all bits.
>> 
>> Instead, store the inverse mask in the preserve mask and then use that
>> on the original value read from the error status so that only the error
>> is cleared.
>> 
>> Fixes: c45ded7e1135 ("mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)")
>
> Good catch!
>
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

Thanks! It looks like Jassi picked up the patch as a fix for v6.18.