From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 676303AAF5D; Wed, 29 Jul 2026 15:23:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785338606; cv=none; b=l8Ki+Eq00TIn8Sr43Z1EdpNZHgD/zNjEWs/0EXnkDgw7WJx06R7LOEN6u6M10pOE1jp/VQe7Wt+/M1j6AyLICwbgBW1frULcjyKccN1bP71DqfAYZqvA+T7n9qjTZLQlMM4AAIPdKT9DSGqVSS4MSU7tHz6QR4FcuYSSSwjU4AQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785338606; c=relaxed/simple; bh=6HpZg3HTf+dCj1Efa/gkF7FZ9+bHwZGO9kLymlTaf9M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VMkGRK9CgQfRXhtLsMknEubEere+1Zo5eEUcxL8mHRlpkDMgJnQGGmjC1h13N1JJY8Py5mdnTtxzxqbGWAYDU/km+eJnOS61GP0vz9grC/7aiOlugvU6tw79lS9Q0pxdKAUXvFFx3t43jMxfOGEcs3s18b/adzZqIK7+qbrBUOw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Yrz7TVUA; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Yrz7TVUA" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56E3A1684; Wed, 29 Jul 2026 08:23:18 -0700 (PDT) Received: from [10.2.212.8] (e134344.arm.com [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A1BAD3F763; Wed, 29 Jul 2026 08:23:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785338602; bh=6HpZg3HTf+dCj1Efa/gkF7FZ9+bHwZGO9kLymlTaf9M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Yrz7TVUAHRSB36VjRm1//NZMBIaL+MHHh4Rv2vuxoIqFgR9IJHuQJ4GmN6eGnE9Oc QwWYI+HfUr5B5cmXFQ7lC6GnrSvXvfHa4kI2FUTg65RlbmZZ4V+akm0y5YYxxhNWlV 8/MwjWb1JWbBgJp19ohf5pZhMWiCh2QmRu87Fe3M= Message-ID: <881a3224-fb19-4ded-ae7e-3f7ae139fe52@arm.com> Date: Wed, 29 Jul 2026 16:23:18 +0100 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Thunderbird Daily Subject: Re: [PATCH v5 09/10] arm_mpam: change error IRQ to use a threaded IRQ handler To: Andre Przywara , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260729134124.2506269-1-andre.przywara@arm.com> <20260729134124.2506269-10-andre.przywara@arm.com> Content-Language: en-US From: Ben Horgan In-Reply-To: <20260729134124.2506269-10-andre.przywara@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Andre, On 7/29/26 14:41, Andre Przywara wrote: > When an MPAM MSC gets into an error condition, it can trigger an error > IRQ. We cannot really do much about those errors, but we at least query > and log the error, then disable MPAM functionality. > > This error report relies on reading the MSC's error status register > (ESR) in the IRQ handler, which is not possible for MPAM-Fb based > MSC accesses, since they involve mailbox routines that might sleep. > The same is true for clearing the interrupt at the source, which > requires an MSC access as well. > > Change the error IRQ to use a threaded IRQ handler, with an empty hard > IRQ routine, and doing all the MSC accesses (to access the status and > disable the IRQ line) in the threaded part. The change is minimal, we > just check for the first MSC access error and bail out early. > Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a > threaded IRQ here. > > Signed-off-by: Andre Przywara > --- > drivers/resctrl/mpam_devices.c | 42 ++++++++++++++++++++++------------ > 1 file changed, 28 insertions(+), 14 deletions(-) > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index abe1e628928f..e535603d2c7d 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -2659,9 +2659,11 @@ static int mpam_disable_msc_ecr(void *_msc) > return 0; > } > > +/* threaded IRQ handler for shared IRQs, to allow MPAM-Fb accesses to sleep */ This comment seems incomplete. The same handler is used for the PPI hardirq. > static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) > { > u64 reg; > + int ret; > u16 partid; > u8 errcode, pmg, ris; > > @@ -2670,13 +2672,19 @@ static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) > &msc->accessibility))) > return IRQ_NONE; > > - mpam_msc_read_esr(msc, ®); > + ret = mpam_msc_read_esr(msc, ®); This is also called for MMIO accesses and the checks in the reads and writes call smp_processor_id() which will give warnings if we are preemptible. There is also a similar to check higher up in this handler. We need to choose in what context we call things based on whether we are using MMIO accesses or MPAM-Fb. Thanks, Ben > + if (ret) { > + pr_err_ratelimited("unknown error irq from msc:%u\n", msc->id); > + > + /* Try out best here ... */ > + goto out_disable; > + } > > errcode = FIELD_GET(MPAMF_ESR_ERRCODE, reg); > if (!errcode) > return IRQ_NONE; > > - /* Clear level triggered irq */ > + /* Clear level triggered irq. Ignore errors, we need to proceed. */ > mpam_msc_clear_esr(msc); > > partid = FIELD_GET(MPAMF_ESR_PARTID_MON, reg); > @@ -2687,19 +2695,19 @@ static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) > msc->id, mpam_errcode_names[errcode], partid, pmg, > ris); > > - /* Disable this interrupt. */ > +out_disable: > + /* Disable this interrupt. Ignore errors, we need to proceed anyway. */ > mpam_disable_msc_ecr(msc); > > - /* Are we racing with the thread disabling MPAM? */ > - if (!mpam_is_enabled()) > - return IRQ_HANDLED; > - > /* > - * Schedule the teardown work. Don't use a threaded IRQ as we can't > - * unregister the interrupt from the threaded part of the handler. > + * Schedule the teardown work. We have to defer it as we can't > + * unregister the interrupt from the threaded part of a handler. > + * Check whether we are racing with the thread disabling MPAM. > */ > - mpam_disable_reason = "hardware error interrupt"; > - schedule_work(&mpam_broken_work); > + if (mpam_is_enabled()) { > + mpam_disable_reason = "hardware error interrupt"; > + schedule_work(&mpam_broken_work); > + } > > return IRQ_HANDLED; > } > @@ -2735,6 +2743,11 @@ static int mpam_register_irqs(void) > /* The MPAM spec says the interrupt can be SPI, PPI or LPI */ > /* We anticipate sharing the interrupt with other MSCs */ > if (irq_is_percpu(irq)) { > + if (msc->iface != MPAM_IFACE_MMIO) { > + dev_err(&msc->pdev->dev, > + "Only MMIO MSCs can use per-CPU interrupts\n"); > + return -EINVAL; > + } > err = request_percpu_irq(irq, &mpam_ppi_handler, > "mpam:msc:error", > msc->error_dev_id); > @@ -2746,9 +2759,10 @@ static int mpam_register_irqs(void) > &_enable_percpu_irq, &irq, > true); > } else { > - err = devm_request_irq(&msc->pdev->dev, irq, > - &mpam_spi_handler, IRQF_SHARED, > - "mpam:msc:error", msc); > + err = devm_request_threaded_irq(&msc->pdev->dev, irq, > + NULL, &mpam_spi_handler, > + IRQF_SHARED | IRQF_ONESHOT, > + "mpam:msc:error", msc); > if (err) > return err; > }