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From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
To: Yisheng Xie <xieyisheng1@huawei.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>
Cc: "joro@8bytes.org" <joro@8bytes.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	Mark Rutland <Mark.Rutland@arm.com>,
	Catalin Marinas <Catalin.Marinas@arm.com>,
	Will Deacon <Will.Deacon@arm.com>,
	Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
	"hanjun.guo@linaro.org" <hanjun.guo@linaro.org>,
	Sudeep Holla <Sudeep.Holla@arm.com>,
	"rjw@rjwysocki.net" <rjw@rjwysocki.net>,
	"lenb@kernel.org" <lenb@kernel.org>,
	Robin Murphy <Robin.Murphy@arm.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
	"tn@semihalf.com" <tn@semihalf.com>,
	"liubo95@huawei.com" <liubo95@huawei.com>,
	"thunder.leizhen@huawei.com" <thunder.leizhen@huawei.com>,
	"gabriele.paoloni@huawei.com" <gabriele.paoloni@huawei.com>,
	nwatters@cod
Subject: Re: [RFCv2 PATCH 00/36] Process management for IOMMU + SVM for SMMUv3
Date: Thu, 12 Oct 2017 13:55:32 +0100	[thread overview]
Message-ID: <8a1e090d-22e8-0295-a53f-bc3b5b7d7971@arm.com> (raw)
In-Reply-To: <c6b7fb4b-4f2b-0d81-8bb5-8fa6b62aca3a@huawei.com>

On 12/10/17 13:05, Yisheng Xie wrote:
[...]
>>>> * An iommu_process can be bound to multiple domains, and a domain can have
>>>>   multiple iommu_process.
>>> when bind a task to device, can we create a single domain for it? I am thinking
>>> about process management without shared PT(for some device only support PASID
>>> without pri ability), it seems hard to expand if a domain have multiple iommu_process?
>>> Do you have any idea about this?
>>
>> A device always has to be in a domain, as far as I know. Not supporting
>> PRI forces you to pin down all user mappings (or just the ones you use for
>> DMA) but you should sill be able to share PT. Now if you don't support
>> shared PT either, but only PASID, then you'll have to use io-pgtable and a
>> new map/unmap API on an iommu_process. I don't understand your concern
>> though, how would the link between process and domains prevent this use-case?
>>
> So you mean that if an iommu_process bind to multiple devices it should create
> multiple io-pgtables? or just share the same io-pgtable?

I don't know to be honest, I haven't thought much about the io-pgtable
case, I'm all about sharing the mm :)

It really depends on what the user (GPU driver I assume) wants. I think
that if you're not sharing an mm with the device, then you're trying to
hide parts of the process to the device, so you'd also want the
flexibility of having different io-pgtables between devices. Different
devices accessing isolated parts of the process requires separate io-pgtables.

>>>> * IOMMU groups share same PASID table. IOMMU groups are a convenient way
>>>>   to cover various hardware weaknesses that prevent a group of device to
>>>>   be isolated by the IOMMU (untrusted bridge, for instance). It's foolish
>>>>   to assume that all PASID implementations will perfectly isolate devices
>>>>   within a bus and functions within a device, so let's assume all devices
>>>>   within an IOMMU group have to share PASID traffic as well. In general
>>>>   there will be a single device per group.
>>>>
>>>> * It's up to the driver implementation to decide where to implement the
>>>>   PASID tables. For SMMU it's more convenient to have a single PASID table
>>>>   per domain. And I think the model fits better with the existing IOMMU
>>>>   API: IOVA traffic is shared by all devices in a domain, so should PASID
>>>>   traffic.
>>> What's the meaning of "share PASID traffic"? PASID space is system-wide,
>>> and a domain can have multiple iommu_process , so a domain can have multiple
>>> PASIDs , one PASID for a iommu_process, right?
> I get what your mean now, thanks for your explain.
> 
>>
>> Yes, I meant that if a device can access mappings for a specific PASID,
>> then other devices in that same domain are also able to access them.
>>
>> A few reasons for this choice in the SMMU:
>> * As all devices in an IOMMU group will be in the same domain and share
>> the same PASID traffic, it encompasses that case. Groups are the smallest
>> isolation granularity, then users are free to choose to put different
>> IOMMU groups in different domains.
>> * For architectures that can have both non-PASID and PASID traffic
>> simultaneously, like the SMMU, it is simpler to reason about PASID tables
>> being a domain, rather than sharing PASID0 within the domain and handling
>> all others per device.
>> * It's the same principle as non-PASID mappings (iommu_map/unmap is on a
>> domain).
>> * It implement the classic example of IOMMU architectures where multiple
>> device descriptors point to the same PASID tables.
>> * It may be desirable for drivers to share PASIDs within a domain, if they
>> are actually using domains for conveniently sharing address spaces between
>> devices. I'm not sure how much this is used as a feature. It does model a
>> shared bus where each device can snoop DMA, so it may be useful.
>>
> 
> I get another question about this design, thinking about the following case:
> 
> If a platform device with PASID ability, e.g. accelerator, which have multiple
> accelerator process units(APUs), it may create multiple virtual devices, one
> virtual device represent for an APU, with the same sid.
> 
> They can be in different groups, however must be in the same domain as this
> design, for domain held the PASID table, right? So how could they be used by
> different guest OS?

If they have the same SID, they will be in the same group as there will be
a single entry in the SMMU stream table. Otherwise, if the virtual devices
can be properly isolated from each other (in the same way as PCI SR-IOV),
they will each have their own SID, can each be in a different IOMMU group
and can be assigned to different guests.

Thanks,
Jean

  reply	other threads:[~2017-10-12 12:50 UTC|newest]

Thread overview: 93+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-06 13:31 [RFCv2 PATCH 00/36] Process management for IOMMU + SVM for SMMUv3 Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 02/36] iommu: Add a process_exit callback for device drivers Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 03/36] iommu/process: Add public function to search for a process Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 09/36] iommu/fault: Allow blocking fault handlers Jean-Philippe Brucker
     [not found]   ` <20171006133203.22803-10-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-11-29  6:15     ` Yisheng Xie
     [not found]       ` <7e1c8ea4-e568-1000-17de-62f8562c7169-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-11-29 15:01         ` Jean-Philippe Brucker
     [not found]           ` <74891e35-17d8-5831-1ebd-18e00ce00d74-5wv7dgnIgG8@public.gmane.org>
2017-11-30  2:45             ` Yisheng Xie
2017-10-06 13:31 ` [RFCv2 PATCH 10/36] vfio: Add support for Shared Virtual Memory Jean-Philippe Brucker
2017-11-24  8:23   ` Bob Liu
2017-11-24 10:58     ` Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 11/36] iommu/arm-smmu-v3: Link domains and devices Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 12/36] dt-bindings: document stall and PASID properties for IOMMU masters Jean-Philippe Brucker
     [not found]   ` <20171006133203.22803-13-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-10-13 19:10     ` Rob Herring
2017-10-16 10:23       ` Jean-Philippe Brucker
     [not found]         ` <e7288f51-1cfa-44ce-e3ce-e9f3daf91579-5wv7dgnIgG8@public.gmane.org>
2017-10-18  2:06           ` Rob Herring
2017-10-06 13:31 ` [RFCv2 PATCH 14/36] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
2017-11-02 12:49   ` Shameerali Kolothum Thodi
2017-11-02 15:51     ` Jean-Philippe Brucker
2017-11-02 17:02       ` Shameerali Kolothum Thodi
2017-11-03  5:45         ` Yisheng Xie
2017-11-03  9:37           ` Jean-Philippe Brucker
2017-11-03  9:39             ` Shameerali Kolothum Thodi
2017-11-06  0:50             ` Yisheng Xie
2017-10-06 13:31 ` [RFCv2 PATCH 15/36] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 16/36] iommu/arm-smmu-v3: Add support for VHE Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 17/36] iommu/arm-smmu-v3: Support broadcast TLB maintenance Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 18/36] iommu/arm-smmu-v3: Add SVM feature checking Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 22/36] iommu/io-pgtable-arm: Factor out ARM LPAE register defines Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 24/36] iommu/arm-smmu-v3: Steal private ASID from a domain Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 25/36] iommu/arm-smmu-v3: Use shared ASID set Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 26/36] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update Jean-Philippe Brucker
2017-12-06  6:51   ` Yisheng Xie
     [not found]     ` <d2ec2e61-f758-0394-41d2-555ae65feb0d-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2017-12-06 11:06       ` Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 27/36] iommu/arm-smmu-v3: Register fault workqueue Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 31/36] iommu/arm-smmu-v3: Add support for PCI ATS Jean-Philippe Brucker
2017-11-16 14:19   ` Bharat Kumar Gogada
     [not found]     ` <BLUPR0201MB150565029F9260A528739ACBA52E0-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-16 15:03       ` Jean-Philippe Brucker
     [not found]         ` <673fda01-2ae0-87e4-637e-fe27096b6be0-5wv7dgnIgG8@public.gmane.org>
2017-11-17  6:11           ` Bharat Kumar Gogada
     [not found]             ` <BLUPR0201MB1505BC86D3838D13F38665E7A52F0-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-17 11:39               ` Jean-Philippe Brucker
2017-10-06 13:31 ` [RFCv2 PATCH 32/36] iommu/arm-smmu-v3: Hook ATC invalidation to process ops Jean-Philippe Brucker
2017-10-06 13:32 ` [RFCv2 PATCH 33/36] iommu/arm-smmu-v3: Disable tagged pointers Jean-Philippe Brucker
     [not found] ` <20171006133203.22803-1-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-10-06 13:31   ` [RFCv2 PATCH 01/36] iommu: Keep track of processes and PASIDs Jean-Philippe Brucker
2017-10-23 11:04     ` Liu, Yi L
2017-10-23 12:17       ` Jean-Philippe Brucker
     [not found]         ` <7aaf9851-9546-f34d-1496-cbeea404abbd-5wv7dgnIgG8@public.gmane.org>
2017-10-25 18:05           ` Raj, Ashok
2017-10-30 10:28             ` Jean-Philippe Brucker
     [not found]     ` <20171006133203.22803-2-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-10-20 23:32       ` Sinan Kaya
2017-11-02 16:20         ` Jean-Philippe Brucker
2017-11-08 17:50       ` Bharat Kumar Gogada
2017-11-09 12:13         ` Jean-Philippe Brucker
     [not found]         ` <BLUPR0201MB150538FDD455F6042803B54FA5560-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-09 12:16           ` Jean-Philippe Brucker
     [not found]             ` <16b6ba80-b15b-b278-0d06-350ae0201e82-5wv7dgnIgG8@public.gmane.org>
2017-11-13 11:06               ` Bharat Kumar Gogada
2017-11-22  3:15     ` Bob Liu
2017-11-22 13:04       ` Jean-Philippe Brucker
     [not found]         ` <42f815ee-2a9a-ac49-2392-5c03c1d4c809-5wv7dgnIgG8@public.gmane.org>
2017-11-23 10:33           ` Bob Liu
2017-10-06 13:31   ` [RFCv2 PATCH 04/36] iommu/process: Track process changes with an mmu_notifier Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 05/36] iommu/process: Bind and unbind process to and from devices Jean-Philippe Brucker
2017-10-11 11:33     ` Joerg Roedel
2017-10-12 11:13       ` Jean-Philippe Brucker
     [not found]         ` <ee7f80e3-ca30-0ee7-53f3-3e57b2b58df6-5wv7dgnIgG8@public.gmane.org>
2017-10-12 12:47           ` Joerg Roedel
     [not found]     ` <20171006133203.22803-6-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-10-21 15:47       ` Sinan Kaya
     [not found]         ` <683a518d-0e22-c855-2416-2e097ec3291d-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-11-02 16:21           ` Jean-Philippe Brucker
2017-11-29  6:08     ` Yisheng Xie
2017-11-29 15:01       ` Jean-Philippe Brucker
2017-11-30  1:11         ` Yisheng Xie
2017-11-30 13:39           ` Jean-Philippe Brucker
2018-01-19  4:52     ` Sinan Kaya
     [not found]       ` <0772e71e-4861-1e7b-f248-88aaba8bf2fc-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-01-19 10:27         ` Jean-Philippe Brucker
2018-01-19 13:07           ` okaya
2017-10-06 13:31   ` [RFCv2 PATCH 06/36] iommu: Extend fault reporting Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 07/36] iommu: Add a fault handler Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 08/36] iommu/fault: Handle mm faults Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 13/36] iommu/of: Add stall and pasid properties to iommu_fwspec Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 19/36] arm64: mm: Pin down ASIDs for sharing contexts with devices Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 20/36] iommu/arm-smmu-v3: Track ASID state Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 21/36] iommu/arm-smmu-v3: Implement process operations Jean-Philippe Brucker
2017-11-09  3:32     ` Yisheng Xie
2017-11-09 12:08       ` Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 23/36] iommu/arm-smmu-v3: Share process page tables Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 28/36] iommu/arm-smmu-v3: Maintain a SID->device structure Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 29/36] iommu/arm-smmu-v3: Add stall support for platform devices Jean-Philippe Brucker
2017-10-06 13:31   ` [RFCv2 PATCH 30/36] ACPI/IORT: Check ATS capability in root complex nodes Jean-Philippe Brucker
2017-10-06 13:32   ` [RFCv2 PATCH 34/36] PCI: Make "PRG Response PASID Required" handling common Jean-Philippe Brucker
     [not found]     ` <20171006133203.22803-35-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-10-06 18:11       ` Bjorn Helgaas
2017-10-06 13:32   ` [RFCv2 PATCH 35/36] iommu/arm-smmu-v3: Add support for PRI Jean-Philippe Brucker
2017-10-06 13:32 ` [RFCv2 PATCH 36/36] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker
2017-10-09  9:49 ` [RFCv2 PATCH 00/36] Process management for IOMMU + SVM for SMMUv3 Yisheng Xie
2017-10-09 11:36   ` Jean-Philippe Brucker
     [not found]     ` <0fecd29e-eaf7-9503-b087-7bfbc251da88-5wv7dgnIgG8@public.gmane.org>
2017-10-12 12:05       ` Yisheng Xie
2017-10-12 12:55         ` Jean-Philippe Brucker [this message]
     [not found]           ` <8a1e090d-22e8-0295-a53f-bc3b5b7d7971-5wv7dgnIgG8@public.gmane.org>
2017-10-12 15:28             ` Jordan Crouse
2017-11-08  1:21           ` Bob Liu
2017-11-08 10:50             ` Jean-Philippe Brucker

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