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[2001:1c00:c0c:fe00:d2ea:f29d:118b:24dc]) by smtp.gmail.com with ESMTPSA id v5sm7020051ejv.114.2020.09.04.13.04.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Sep 2020 13:04:06 -0700 (PDT) Subject: Re: [PATCH] pinctrl: cherryview: Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs To: Andy Shevchenko Cc: Mika Westerberg , Linus Walleij , linux-gpio@vger.kernel.org, linux-acpi@vger.kernel.org References: <20200904172141.180363-1-hdegoede@redhat.com> <20200904180947.GL1891694@smile.fi.intel.com> From: Hans de Goede Message-ID: <993251db-acac-65f3-56fb-c35044ab8080@redhat.com> Date: Fri, 4 Sep 2020 22:04:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200904180947.GL1891694@smile.fi.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Hi, On 9/4/20 8:09 PM, Andy Shevchenko wrote: > On Fri, Sep 04, 2020 at 07:21:41PM +0200, Hans de Goede wrote: >> One some devices the GPIO should output the inverted value from what > >> Fixes: a7d4b171660c ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices") > > Hans, a side note. Can you clean up that driver using ACPI GPIO quirks and the > idea that IRQ line will be retrieved in client->irq? Nope, the chip uses the IRQ line in a bi-directional manner, when the chip is reset (by us) the IRQ line is a bootstrap pin and we need to drive it either high or low to make sure the chip re-appears on the same i2c-address as it had before. So we need the get gpiod and then call gpiod_to_irq abstraction so that we also have the gpiod to call allow calling gpiod_direction_input() and gpiod_direction_output() on the irq pin. And to make things more interesting on some generations x86 hw (apollo lake) the IRQ is actually listed as an Interrupt resource in the ACPI device resources (_CRS) and there are GDIX specific ACPI methods on the ACPI device which directly poke the GPIO chip to allow setting it high/low (for during reset) or config it as input. So the goodix.c has its own internal abstraction around gpiod_direction_input(() and gpiod_direction_output() for controlling the IRQ pin which does different things on different x86 hw generations (while also maintaining device-tree compat). So all in all I'm happy that we have this all working atm (and it also is reasonably clean already IMHO) and I would rather not muck with this. Regards, Hans