From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dan Williams Subject: Re: [PATCHv4 06/13] acpi/hmat: Register processor domain to its memory Date: Thu, 17 Jan 2019 09:01:27 -0800 Message-ID: References: <20190116175804.30196-1-keith.busch@intel.com> <20190116175804.30196-7-keith.busch@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: "Rafael J. Wysocki" Cc: Keith Busch , Linux Kernel Mailing List , ACPI Devel Maling List , Linux Memory Management List , Greg Kroah-Hartman , Dave Hansen List-Id: linux-acpi@vger.kernel.org On Thu, Jan 17, 2019 at 4:11 AM Rafael J. Wysocki wrote: > > On Wed, Jan 16, 2019 at 6:59 PM Keith Busch wrote: > > > > If the HMAT Subsystem Address Range provides a valid processor proximity > > domain for a memory domain, or a processor domain with the highest > > performing access exists, register the memory target with that initiator > > so this relationship will be visible under the node's sysfs directory. > > > > Since HMAT requires valid address ranges have an equivalent SRAT entry, > > verify each memory target satisfies this requirement. > > What exactly will happen after this patch? > > There will be some new directories under > /sys/devices/system/node/nodeX/ if all goes well. Anything else? When / if the memory randomization series [1] makes its way upstream there will be a follow-on patch to enable that randomization based on the presence of a memory-side cache published in the HMAT. [1]: https://lwn.net/Articles/767614/