From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0BF9C4320A for ; Wed, 11 Aug 2021 13:41:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A534560FD9 for ; Wed, 11 Aug 2021 13:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231867AbhHKNmJ (ORCPT ); Wed, 11 Aug 2021 09:42:09 -0400 Received: from mga06.intel.com ([134.134.136.31]:7976 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230425AbhHKNmJ (ORCPT ); Wed, 11 Aug 2021 09:42:09 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10072"; a="276158943" X-IronPort-AV: E=Sophos;i="5.84,313,1620716400"; d="scan'208";a="276158943" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2021 06:41:45 -0700 X-IronPort-AV: E=Sophos;i="5.84,313,1620716400"; d="scan'208";a="503499266" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2021 06:41:42 -0700 Received: from andy by smile with local (Exim 4.94.2) (envelope-from ) id 1mDoUB-007uxQ-Nh; Wed, 11 Aug 2021 16:41:35 +0300 Date: Wed, 11 Aug 2021 16:41:35 +0300 From: Andy Shevchenko To: Linus Walleij Cc: linux-kernel , "open list:GPIO SUBSYSTEM" , ACPI Devel Maling List , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H. Peter Anvin" , Hans de Goede , Bartosz Golaszewski , "Rafael J. Wysocki" Subject: Re: [PATCH v1 1/1] x86/platform: Increase maximum GPIO number for X86_64 Message-ID: References: <20210806143711.37553-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Wed, Aug 11, 2021 at 03:14:59PM +0200, Linus Walleij wrote: > On Fri, Aug 6, 2021 at 4:44 PM Andy Shevchenko > wrote: > > > By default the 512 GPIOs is a maximum on any x86 platform. > > With, for example, Intel Tiger Lake-H the SoC based controller > > occupies up to 480 pins. This leaves only 32 available for > > GPIO expanders or other drivers, like PMIC. Hence, bump the > > maximum GPIO number to 1024 for X86_64 and leave 512 for X86_32. > > > > Signed-off-by: Andy Shevchenko > > Looks reasonable to me. > The goal with the whole descriptor refactoring is to get this > completely dynamic but it turns out to take forever. It is as it > is. > > Reviewed-by: Linus Walleij Thanks! Rafael, can you please review this? -- With Best Regards, Andy Shevchenko