From: "Gautham R. Shenoy" <gautham.shenoy@amd.com>
To: "zhenglifeng (A)" <zhenglifeng1@huawei.com>
Cc: rafael@kernel.org, lenb@kernel.org, robert.moore@intel.com,
viresh.kumar@linaro.org, mario.limonciello@amd.com,
ray.huang@amd.com, pierre.gondois@arm.com,
acpica-devel@lists.linux.dev, linux-acpi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linuxarm@huawei.com, jonathan.cameron@huawei.com,
zhanjie9@hisilicon.com, lihuisong@huawei.com,
hepeng68@huawei.com, fanghao11@huawei.com
Subject: Re: [PATCH v4 6/6] cpufreq: CPPC: Support for autonomous selection in cppc_cpufreq
Date: Thu, 16 Jan 2025 11:43:36 +0530 [thread overview]
Message-ID: <Z4ijkAFOMtVAOY6u@BLRRASHENOY1.amd.com> (raw)
In-Reply-To: <f89fc07a-1c65-4d1e-9ad8-76c6c9a15b25@huawei.com>
On Thu, Jan 16, 2025 at 09:26:37AM +0800, zhenglifeng (A) wrote:
> On 2025/1/15 22:51, Gautham R. Shenoy wrote:
>
> > Hello Lifeng,
> >
> >
> > On Mon, Jan 13, 2025 at 08:21:04PM +0800, Lifeng Zheng wrote:
> >> Add sysfs interfaces for CPPC autonomous selection in the cppc_cpufreq
> >> driver.
> >>
> >
> > [..snip..]
> >
> >> diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
> >> index bd8f75accfa0..ea6c6a5bbd8c 100644
> >> --- a/drivers/cpufreq/cppc_cpufreq.c
> >> +++ b/drivers/cpufreq/cppc_cpufreq.c
> >> @@ -814,10 +814,119 @@ static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf)
> >>
> >> return cpufreq_show_cpus(cpu_data->shared_cpu_map, buf);
> >> }
> >> +
> >> +static ssize_t show_auto_select(struct cpufreq_policy *policy, char *buf)
> >> +{
> >> + bool val;
> >> + int ret;
> >> +
> >> + ret = cppc_get_auto_sel(policy->cpu, &val);
> >> +
> >> + /* show "<unsupported>" when this register is not supported by cpc */
> >> + if (ret == -EOPNOTSUPP)
> >> + return sysfs_emit(buf, "%s\n", "<unsupported>");
> >> +
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return sysfs_emit(buf, "%d\n", val);
> >> +}
> >> +
> >> +static ssize_t store_auto_select(struct cpufreq_policy *policy,
> >> + const char *buf, size_t count)
> >> +{
> >> + bool val;
> >> + int ret;
> >> +
> >> + ret = kstrtobool(buf, &val);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + ret = cppc_set_auto_sel(policy->cpu, val);
> >
> > When the auto_select register is not supported, since
> > cppc_set_reg_val() doesn't have the !CPC_SUPPORTED(reg) check, that
> > function won't return an error, and thus this store function won't
> > return an error either. Should there be a !CPC_SUPPORTED(reg) check in
> > cppc_set_reg_val() as well? Or should the store function call
> > cppc_get_auto_sel() to figure out if the register is supported or not?
>
> In patch 2, I have this check in cppc_set_reg_val():
>
> + /* if a register is writeable, it must be a buffer */
> + if ((reg->type != ACPI_TYPE_BUFFER) ||
> + (IS_OPTIONAL_CPC_REG(reg_idx) && IS_NULL_REG(®->cpc_entry.reg))) {
> + pr_debug("CPC register (reg_idx=%d) is not supported\n", reg_idx);
> + return -EOPNOTSUPP;
> + }
>
> If a register is not a cpc supported one, it must be either an integer type
> or a null one. So it won't pass this check I think.
Ah, I see. In that case, you can remove the cppc_get_auto_sel() in
shmem_init_perf() function in amd_pstate.c (in Patch 5/6) from the
following snippet. The auto_sel value is nowhere used in the rest of
the code.
@@ -399,6 +399,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata)
{
struct cppc_perf_caps cppc_perf;
u64 numerator;
+ bool auto_sel; <--- Not needed.
int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
if (ret)
@@ -420,7 +421,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata)
if (cppc_state == AMD_PSTATE_ACTIVE)
return 0;
- ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf); <--- Not needed.
+ ret = cppc_get_auto_sel(cpudata->cpu, &auto_sel); <--- Not needed.
if (ret) { <--- Not needed.
pr_warn("failed to get auto_sel, ret: %d\n", ret); <--- Not needed.
--
Thanks and Regards
gautham.
next prev parent reply other threads:[~2025-01-16 6:13 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-13 12:20 [PATCH v4 0/6] Support for autonomous selection in cppc_cpufreq Lifeng Zheng
2025-01-13 12:20 ` [PATCH v4 1/6] ACPI: CPPC: Add IS_OPTIONAL_CPC_REG macro Lifeng Zheng
2025-01-14 13:27 ` Rafael J. Wysocki
2025-01-15 7:52 ` zhenglifeng (A)
2025-01-13 12:21 ` [PATCH v4 2/6] ACPI: CPPC: Add cppc_get_reg_val and cppc_set_reg_val function Lifeng Zheng
2025-01-14 17:41 ` Rafael J. Wysocki
2025-01-15 8:10 ` zhenglifeng (A)
2025-01-13 12:21 ` [PATCH v4 3/6] ACPI: CPPC: Add macros to generally implement registers getting and setting functions Lifeng Zheng
2025-01-14 17:58 ` Rafael J. Wysocki
2025-01-15 8:58 ` zhenglifeng (A)
2025-01-15 11:12 ` Rafael J. Wysocki
2025-01-16 1:12 ` zhenglifeng (A)
2025-01-13 12:21 ` [PATCH v4 4/6] ACPI: CPPC: Refactor register value get and set ABIs Lifeng Zheng
2025-01-13 12:21 ` [PATCH v4 5/6] ACPI: CPPC: Add autonomous selection ABIs Lifeng Zheng
2025-01-14 18:24 ` Rafael J. Wysocki
2025-01-15 9:16 ` zhenglifeng (A)
2025-01-13 12:21 ` [PATCH v4 6/6] cpufreq: CPPC: Support for autonomous selection in cppc_cpufreq Lifeng Zheng
2025-01-15 14:51 ` Gautham R. Shenoy
2025-01-16 1:26 ` zhenglifeng (A)
2025-01-16 6:13 ` Gautham R. Shenoy [this message]
2025-01-16 8:01 ` zhenglifeng (A)
2025-01-16 14:33 ` Gautham R. Shenoy
2025-01-16 11:39 ` Russell Haley
2025-01-17 3:11 ` zhenglifeng (A)
2025-01-17 14:30 ` Mario Limonciello
2025-01-20 3:15 ` zhenglifeng (A)
2025-01-20 14:49 ` Pierre Gondois
2025-01-20 17:44 ` Mario Limonciello
2025-01-21 2:42 ` zhenglifeng (A)
2025-01-23 16:46 ` Srinivas Pandruvada
2025-01-23 17:05 ` Mario Limonciello
2025-01-24 3:53 ` zhenglifeng (A)
2025-01-24 14:18 ` srinivas pandruvada
2025-02-05 6:13 ` zhenglifeng (A)
2025-01-24 14:32 ` Russell Haley
2025-02-05 6:13 ` zhenglifeng (A)
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