Re: [PATCH v4 3/3] irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing

Marc Zyngier
2024-01-08T09:52:23Z

On Mon, 08 Jan 2024 09:43:23 +0000,
Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Thu, Jan 04, 2024 at 11:12:28AM +0000, Marc Zyngier wrote:
> > On Wed, 27 Dec 2023 11:00:38 +0000,
> > Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> > >
> > > The GIC architecture specification defines a set of registers
> > > for redistributors and ITSes that control the sharebility and
> > > cacheability attributes of redistributors/ITSes initiator ports
> > > on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER,
> > > GITS_BASER<n>).
> > >
> > > Architecturally the GIC provides a means to drive shareability
> > > and cacheability attributes signals and related IWB/OWB/ISH barriers
> >
> > IWB/OWB *barriers*? Unless you're talking about something else,
> > IWB/OWB refers to cacheability, and only that.
>
> Yes, it should be expressed differently. Unfortunately this sentence made
> it into the kernel with the DT counterpart - commit 3a0fff0fb6a3 log,
> apologies.

Oh well. At least please clean this one up when you repost.

[...]

> > > + if (!madt_read) {
> > > + madt_read = true;
> >
> > Huh. Why do we need this hack? What's the issue with accessing the
> > MADT? Can it disappear from under our feet? While we're walking it?
>
> It is an awkward attempt at stashing the revision instead of
> calling acpi_get_table() repeatedly (and from multiple files
> for the same reason - ie get an MADT rev number).
>
> Side note: get_madt_table() does the same thing and I followed
> it - I am not sure it is very helpful either (or maybe
> there is something I don't know behind that reasoning).

This was introduced as part of 149fe9c293f76, as a cleanup. Not a
great move IMHO.

M.

--
Without deviation from the norm, progress is not possible.