From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6DAAF56440; Thu, 2 May 2024 10:12:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714644772; cv=none; b=gG6xMiBnnuL1uvZaml2RtKVU4IMqZFNbKm/ffSoT3jcTrPv4yc2l12GkXBs/dvuGaeyFZ+srS11kLYEKN4MEmAa7j8OLyx+X2sPphjJyEXIkC7FnZ2ht36O5tvOsakI4XwBGYQWPq3ucOi40NhQExFHrJB9vqZgpgeuGcZys6L8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714644772; c=relaxed/simple; bh=IJLO7lK4MuUZ4lhoA53IDhYlXK4mZYX5Rc8GQjN3+24=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ubIYNkTy4zK26p6WpEXeOKsOzYzYtLZA3nxjBFBEX+js7+3GVH5Em3UAEvO7nfxmcxHJEy4+R5NBLRJ6sx9p1JO2AZ5PygTQmVvnKYO1WEzji3gTMGg/2pp9Pe68WpDuqYk1EI2ed/zjaMkuNFQt7xRD4LdCcvG/vw3cjDxyY5E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 073A62F4; Thu, 2 May 2024 03:13:15 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F12A53F793; Thu, 2 May 2024 03:12:45 -0700 (PDT) Date: Thu, 2 May 2024 11:12:43 +0100 From: Sudeep Holla To: Andy Shevchenko Cc: Sunil V L , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev, Sudeep Holla , Catalin Marinas , Will Deacon , Paul Walmsley , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Subject: Re: [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function Message-ID: References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> <20240501121742.1215792-4-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, May 02, 2024 at 03:32:25PM +0530, Sunil V L wrote: > On Thu, May 02, 2024 at 12:24:14PM +0300, Andy Shevchenko wrote: > > On Wed, May 01, 2024 at 05:47:28PM +0530, Sunil V L wrote: > > > Add a new function for RISC-V to do any architecture specific > > > initialization. This function will be used to create platform devices > > > like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init(). > > > > What is the special about this architecture that it requires a separate > > initialization that is _not_ going to be in other cases? > > Please, elaborate. > > > This init function will be used to create GSI mapping structures and in > future may be others like iommu. Like I mentioned, ARM already has > similar function acpi_arm_init(). So, it is not new right? > Just to add: This is to initialise everything around all the arch specific tables which you will not have on any other architectures. We could execute on all architectures but the tables will never be found. The main point is why do we want to do that if we can optimise and skip on all other archs. -- Regards, Sudeep