Re: [PATCH v3 3/9] ACPI/IORT: Support CANWBS memory access flag

Hanjun Guo
2024-10-10T07:45:12Z

On 2024/10/10 0:23, Jason Gunthorpe wrote:
> From: Nicolin Chen<nicolinc@nvidia.com>
>
> The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
> Access Flag field in the Memory Access Properties table, mainly for a PCI
> Root Complex.
>
> This CANWBS defines the coherency of memory accesses to be not marked IOWB
> cacheable/shareable. Its value further implies the coherency impact from a
> pair of mismatched memory attributes (e.g. in a nested translation case):
> 0x0: Use of mismatched memory attributes for accesses made by this
> device may lead to a loss of coherency.
> 0x1: Coherency of accesses made by this device to locations in
> Conventional memory are ensured as follows, even if the memory
> attributes for the accesses presented by the device or provided by
> the SMMU are different from Inner and Outer Write-back cacheable,
> Shareable.
>
> Note that the loss of coherency on a CANWBS-unsupported HW typically could
> occur to an SMMU that doesn't implement the S2FWB feature where additional
> cache flush operations would be required to prevent that from happening.
>
> Add a new ACPI_IORT_MF_CANWBS flag and set IOMMU_FWSPEC_PCI_RC_CANWBS upon
> the presence of this new flag.
>
> CANWBS and S2FWB are similar features, in that they both guarantee the VM
> can not violate coherency, however S2FWB can be bypassed by PCI No Snoop
> TLPs, while CANWBS cannot. Thus CANWBS meets the requirements to set
> IOMMU_CAP_ENFORCE_CACHE_COHERENCY.
>
> Architecturally ARM has expected that VFIO would disable No Snoop through
> PCI Config space, if this is done then the two would have the same
> protections.

Acked-by: Hanjun Guo <guohanjun@huawei.com>

Thanks
Hanjun