Re: [PATCH v3 2/9] ACPICA: IORT: Update for revision E.f

Hanjun Guo
2024-10-10T01:48:59Z

On 2024/10/10 0:23, Jason Gunthorpe wrote:
> From: Nicolin Chen <nicolinc@nvidia.com>
>
> ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab
>
> The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
> Access Flag field in the Memory Access Properties table, mainly for a PCI
> Root Complex.
>
> This CANWBS defines the coherency of memory accesses to be not marked IOWB
> cacheable/shareable. Its value further implies the coherency impact from a
> pair of mismatched memory attributes (e.g. in a nested translation case):
> 0x0: Use of mismatched memory attributes for accesses made by this
> device may lead to a loss of coherency.
> 0x1: Coherency of accesses made by this device to locations in
> Conventional memory are ensured as follows, even if the memory
> attributes for the accesses presented by the device or provided by
> the SMMU are different from Inner and Outer Write-back cacheable,
> Shareable.
>

Acked-by: Hanjun Guo <guohanjun@huawei.com>

Thanks
Hanjun