From: Demi Marie Obenour <demiobenour@gmail.com>
To: "Xiaoyao Li" <xiaoyao.li@intel.com>,
"Sohil Mehta" <sohil.mehta@intel.com>,
"David Woodhouse" <dwmw2@infradead.org>,
x86@kernel.org, "Dave Hansen" <dave.hansen@linux.intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Jürgen Gross" <jgross@suse.com>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
xen-devel <xen-devel@lists.xenproject.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>, "H . Peter Anvin" <hpa@zytor.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Andy Lutomirski <luto@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Jean Delvare <jdelvare@suse.com>,
Guenter Roeck <linux@roeck-us.net>,
Zhang Rui <rui.zhang@intel.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
David Laight <david.laight.linux@gmail.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org,
kvm@vger.kernel.org, Xin Li <xin@zytor.com>
Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks
Date: Sun, 24 Aug 2025 18:39:05 -0400 [thread overview]
Message-ID: <a57a9878-893c-41ab-8380-a0ac9e736752@gmail.com> (raw)
In-Reply-To: <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com>
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On 8/21/25 21:46, Xiaoyao Li wrote:
> On 8/22/2025 3:43 AM, Sohil Mehta wrote:
>> On 8/21/2025 12:34 PM, Sohil Mehta wrote:
>>> On 8/21/2025 6:15 AM, David Woodhouse wrote:
>>>
>>>> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
>>>> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
>>>> explicitly append ',+invtsc' to the existing '-cpu host' on its command
>>>> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
>>>>
>>>
>>> Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
>>> the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
>>> based on the Family-model instead of the CPUID enumeration which may
>>> have hid the issue.
>>>
>>
>> Correction:
>> s/instead/as well as
>>
>>> From my initial look at the QEMU implementation, this seems intentional.
>>>
>>> QEMU considers Invariant TSC as un-migratable which prevents it from
>>> being exposed to migratable guests (default).
>>> target/i386/cpu.c:
>>> [FEAT_8000_0007_EDX]
>>> .unmigratable_flags = CPUID_APM_INVTSC,
>>>
>>> Can you please try '-cpu host,migratable=off'?
>>
>> This is mainly to verify. If confirmed, I am not sure what the long term
>> solution should be.
>
> yeah. It's the intentional behavior of QEMU.
>
> Invariant TSC is ummigratable unless users explicitly configures the TSC
> frequency, e.g., "-cpu host,tsc-frequency=xxx". Because the TSC
> frequency is by default the host's frequency if no "tsc-frequency"
> specified, and it will change when the VM is migrated to a host with a
> different TSC frequency.
>
> It's the specific behavior/rule of QEMU. We just need to keep it in
> mind. If we want to expose invariant TSC to the guest with QEMU's "-cpu
> host", we can either:
> 1) explicitly configure the "tsc-frequency", or
> 2) explicitly turn off "migratable"
Could the TSC frequency be included in the migration stream?
--
Sincerely,
Demi Marie Obenour (she/her/hers)
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next prev parent reply other threads:[~2025-08-24 22:39 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-19 18:41 [PATCH v3 00/15] Prepare for new Intel Family numbers Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 01/15] x86/apic: Fix 32-bit APIC initialization for extended Intel Families Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 02/15] x86/cpu/intel: Fix the movsl alignment preference for extended Families Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 03/15] x86/microcode: Update the Intel processor flag scan check Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 04/15] x86/mtrr: Modify a x86_model check to an Intel VFM check Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 05/15] x86/cpu/intel: Replace early Family 6 checks with VFM ones Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 06/15] x86/cpu/intel: Replace Family 15 " Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 07/15] x86/cpu/intel: Replace Family 5 model " Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 08/15] x86/acpi/cstate: Improve Intel Family model checks Sohil Mehta
2025-02-20 19:20 ` Rafael J. Wysocki
2025-02-19 18:41 ` [PATCH v3 09/15] x86/smpboot: Remove confusing quirk usage in INIT delay Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 10/15] x86/smpboot: Fix INIT delay assignment for extended Intel Families Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 11/15] x86/cpu/intel: Fix fast string initialization for extended Families Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 12/15] x86/pat: Replace Intel x86_model checks with VFM ones Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks Sohil Mehta
2025-08-21 13:15 ` David Woodhouse
2025-08-21 19:34 ` Sohil Mehta
2025-08-21 19:43 ` Sohil Mehta
2025-08-21 20:09 ` David Woodhouse
2025-08-22 1:46 ` Xiaoyao Li
2025-08-24 22:39 ` Demi Marie Obenour [this message]
2025-02-19 18:41 ` [PATCH v3 14/15] perf/x86: Simplify Intel PMU initialization Sohil Mehta
2025-02-19 20:10 ` Liang, Kan
2025-02-19 20:31 ` Sohil Mehta
2025-02-19 20:45 ` Liang, Kan
2025-02-27 0:16 ` [PATCH v3.1 " Sohil Mehta
2025-02-19 18:41 ` [PATCH v3 15/15] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta
2025-02-19 20:11 ` Liang, Kan
2025-03-17 17:09 ` [PATCH v3 00/15] Prepare for new Intel Family numbers Sohil Mehta
2025-03-18 18:35 ` Ingo Molnar
2025-03-18 19:10 ` Sohil Mehta
2025-03-18 20:13 ` Ingo Molnar
2025-03-19 15:53 ` Sohil Mehta
2025-03-19 19:46 ` Ingo Molnar
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