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[34.124.129.10]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6eebe95sm83922b3a.36.2026.03.10.13.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 13:00:54 -0700 (PDT) Date: Tue, 10 Mar 2026 20:00:48 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, jgg@nvidia.com, rafael@kernel.org, lenb@kernel.org, kees@kernel.org, baolu.lu@linux.intel.com, smostafa@google.com, Alexander.Grest@microsoft.com, kevin.tian@intel.com, miko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, vsethi@nvidia.com Subject: Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts Message-ID: References: Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Mar 10, 2026 at 12:51:51PM -0700, Nicolin Chen wrote: > On Tue, Mar 10, 2026 at 07:16:02PM +0000, Pranjal Shrivastava wrote: > > On Wed, Mar 04, 2026 at 09:21:42PM -0800, Nicolin Chen wrote: > > > + /* > > > + * ATC timeout indicates the device has stopped responding to coherence > > > + * protocol requests. The only safe recovery is a reset to flush stale > > > + * cached translations. Note that pci_reset_function() internally calls > > > + * pci_dev_reset_iommu_prepare/done() as well and ensures to block ATS > > > + * if PCI-level reset fails. > > > + */ > > > + if (!pci_reset_function(pdev)) { > > > > I'm a little uncomfortable with this, why is an IOMMU driver poking into > > the PCI mechanics? I agree that a reset might be the right thing to do > > here but we wouldn't want the IOMMU driver to trigger it.. Ideally, we'd > > need a mechanism that bubbles up fatal IOMMU faults to the PCI core and > > let it decide/perform the reset. Maybe this could mean adding another op > > to struct pci_error_handlers or something like that? > > Robin/Jason already had similar remarks (to most of your other > comments as well). I have acked their comments, and am already > reworking on these. > Yea just saw those discussions as well, replied before seeing those. > > > + /* > > > + * If reset succeeds, set BME back. Otherwise, fence the system > > > + * from a faulty device, in which case user will have to replug > > > + * the device to invoke pci_set_master(). > > > + */ > > > + pci_dev_lock(pdev); > > > > Why are we using spinlock_irqsave across the worker? Also, why does > > atc_recovery.lock have to be a spinlock? The workers run in process > > context, and I also don't see anyone else take the atc_recovery.lock? > > I guess mutex would be okay here, since there is no other place > access the linked list. Pairing a linked list with a spinlock is > just a common practice.. > Ack agreed. No problem with the type of the lock, just questioning the choice to use spinlock_irqsave et al since I don't believe this could be in interrupt context. > > Why does it need to be irq-safe? If this can somehow run in irq context, > > we also seem to be using pci_dev_lock and streams_mutex across the > > worker? > > pci_dev_lock was to fence race on the PCI level. Yet, the entire > BME call is probably not a good idea. So, dropping that means we > won't need pci_dev_lock. > Ack. > > Mixing mutexes with spinlocks is brittle and invites > > "sleep-while-atomic" bugs in future refactors.. > > Either streams_mutex or atc_recovery.lock was scoped for only a > few lines each section. Each was released before the other one > was taken. Where is the "mixing" or "sleep-while-atomic" case? The case doesn't exist yet, I meant it as a warning against future re-factors, since I didn't see the need to use a spinlock here, I didn't understand why couldn't all 3 be mutexes when the existing 2 already were. Praan