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Wed, 18 Mar 2026 18:15:17 -0700 Date: Wed, 18 Mar 2026 18:15:16 -0700 From: Nicolin Chen To: Samiullah Khawaja CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 4/7] iommu/arm-smmu-v3: Mark ATC invalidate timeouts via lockless bitmap Message-ID: References: <0c5525367cc67ccc84a675544d1d9f8462704065.1773774441.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06B:EE_|DS7PR12MB8289:EE_ X-MS-Office365-Filtering-Correlation-Id: b474b95c-2f2d-4dba-c491-08de85550720 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: QJ7I5poPHBFYn7flxFnVBOSeD2SGAVgWG+BM68QsxI3bJ1uK3ZpbYdo04fpCswqdu1w3M9bGTH/sR+iOXvFgmvi/aq8vQN04cv6ROVk6RYoHzgVvwnzMeXAmMnLKqVvGSx69qeJ6i2UF+VGpOv6939bzGgRpB8KjkulbgFTcJfB5tQ4x8kcAog2UKVq63Z7UFy9rBHwKKAHELyVGRTknjIj+QImVNAf4DU7hQmnJNRgcJuaXjoHQf8h0aIkaRESw74mqiDhnRHKNFfDGQraIRKBZoUDYv4Q8BCe4ylEcp2kj2WmiP1cuL0MFtZwzHJm9NIAjRDPwlJkbV40hDQ5a+UWPq0Op+VRzTX3UbjU2EXRrayMIE7ttwikEOKyD21kJ43pweA6qubSJngmNyjG5RcfsK2CLw6OAWg3jTtS2MF8bUqYkK6AtedquPSa+LldqNoyb4wt8M9ZMHITAsk1Iww6POkNJUll8m2FQE7Gsd5DS5Sa1LwN0zX/VttTXhg57I81msVZfaDZ//9Ly+f8dI5Xh2LO3gcclO1FaC1KcVn0tbn8/98uGHnlHX72p2uUiqzx+FbyVWCB7vC7ZEbXuV1yDy9WiTWVF2V0J17BJIK8p/+hYq94z2kvaXuJWA3lRBJEgTFW6ibzd+KA5baX+VyqlyggNL37nM/c2TQqSyxYbE2D6EbLSF66pPT4mA3LlSFLmdaW27MzHRDyLwmbZtqRaqDoLojzegHacQrnBP382pIqEYcuYTqCtVPrsJUtSlTl5+Ov8bgjjz4+gEW3izg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: C7iiV64at77tipElzHKdGRNY+utd1rBPo5beSrA9oOYb5z4aTFt1OvM9JWLfMpQ2B/HM03xoZL9PSCqrnGOCImC7CVc/mQsfIH0CgXT0LZg80Z3iPrWMWHZudyH9ly6LbtlwimteumeytFmfHgQ3AJYGX9mbIr4kJa5xRJioanQwmG8IcAKWCJrZ9lG052tvp9UlzxzqeP8FG9IRGSYaoZnhyVsAokgHLNEkldrmPjdsD69wvBWElBqmZY7MwIG5538FFSEadYRHHzvRM2HlXxBwrEqgekrI/VQNAosIi5S6gd5/BzKgVFD0CYDtENLsoBNo1F85tWOSglJh8NmeGMDYX6jcvUcYdBvCdcgrP3tU28o1FWARYTlb7aGuSz1cXSFr9I7x/Re4AUKxM3Y/XKnN4NQaR0kyOgRv6Ja9U3Sv0F5L6Lj617Sw9aVuzsGH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 01:15:36.9700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b474b95c-2f2d-4dba-c491-08de85550720 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06B.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8289 On Thu, Mar 19, 2026 at 12:08:04AM +0000, Samiullah Khawaja wrote: > On Wed, Mar 18, 2026 at 04:23:53PM -0700, Nicolin Chen wrote: > > If the software times out first at 1s, it means the CMDQ is still > > pending on wait for the completion of ATC invalidation. Then, the > > caller sees -ETIMEOUT and tries to bisect the ATC batch or update > > the STE directly, either of which involves CMDQ. But CMDQ has not > > recovered yet. > > > > Then, in case of a batch, all the reties could timeout again. So, > > it will fail to identify which device is truly broken. This would > > end badly by blindly disabling all the devices in the batch. Also > > the disabling calls require CMDQ too, so they might fail as well. > > Yes, looking at VT-d currently and the queue length is 256 and this > spirals out of control quickly. > > > > Thus, partially to answer the question, in case software timeout, > > I am afraid that we can hardly do anything.. :-/ > > Agreed. > > Do you think we can maybe document this somewhere? Maybe add to the > cover letter? Yes. I will add a note inline as well where software times out. > > This means I need to set a different return code for ATC timeouts > > v.s. software timeouts. > > > > Also, there is another problem: when PCI CTO finally reaches, the > > GERROR ISR will set atc_sync_timeouts but nobody will clear it.. > > So, before calling arm_smmu_cmdq_issue_cmdlist(), we need to make > > sure there is no dirty bit on the bitmap too. > > Yes, Just to confirm, do you think this needs to be handled regardless > whether we handle the software timeout for the ATC invalidation? > Basically to cleanup the bit on bitmap. I don't see a reason not to. I think the next issuer who sees a dirty slot in the bitmap will not have any idea about that ATC timeout (batch). Basically the previous issuer was returned and the batch is gone. So, it can do nothing but clear the slot in the bitmap and move forward. Nicolin