From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 688BC471D1C; Mon, 5 Oct 2026 11:07:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791198474; cv=none; b=QpaQfISYg/T7cfLucW2AcgigRvWFR4jTSoHfSG3yfJjMsb33iLMugSnqlvVPQMzNCXLbr/iWIMPMw3eY0OteQLe/1QTSNBKOGQCNvxkWEk3FbF7WRErsjXAK9AKxh3Fnsbr3eKuap65Jzs8+37NlUL0oKPMxqV+EsOCXzSHM/UM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791198474; c=relaxed/simple; bh=OstHisGp7P6hgz4/0D89NdgTFhwBoAjGYPB++ZUdrsQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Qm4USnRHf/q9mykQQSfZ9IvBMfr77RvYidb8lOhc+srxQOMlNrV6K+ZrzvvmCXZab7mEGfWEQEdytchxFv5sbcdjx1EVWdfCWe0TX5XmJ2lxjWs9rhuVbg8Hp58QdfFJby5DU6c+A3YucmhHI2YZKsIgwFYTEpq7zXiTWXEI0pE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=huznAKYd; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="huznAKYd" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81EA2152B; Mon, 5 Oct 2026 04:07:49 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9F9B13F86F; Mon, 5 Oct 2026 04:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1791198472; bh=OstHisGp7P6hgz4/0D89NdgTFhwBoAjGYPB++ZUdrsQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=huznAKYddU0oZFKAUlCcQ1STeT/7wXvr3I03BhqGvib3xpajTRxhfLH9R4n0xbL3S kIEIw7UozOwAKAYis3taxahTMvipmp7uuojl2U657r8N7zaBJ5NTsf4aP8uJ8+p+Rb BYYgwF3ME4VdyiRufVFi72RJCpQxDxT6c94/F8TA= Date: Mon, 5 Oct 2026 12:07:46 +0100 From: Catalin Marinas To: Zi Yan Cc: Kristina =?utf-8?Q?Mart=C5=A1enko?= , linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, kvmarm@lists.linux.dev, linux-efi@vger.kernel.org, Will Deacon , Mark Rutland , Ryan Roberts , David Hildenbrand , Lorenzo Stoakes , Linu Cherian , Anshuman Khandual , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Ard Biesheuvel , Ilias Apalodimas , linux-mm@kvack.org Subject: Re: [RFC 00/12] arm64: Add support for TLBI domains Message-ID: References: <20261001110655.461473-1-kristina.martsenko@arm.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sun, Oct 04, 2026 at 02:06:48PM -0400, Zi Yan wrote: > On Thu Oct 1, 2026 at 7:06 AM EDT, Kristina Martšenko wrote: > > This series allows the kernel to use TLBI domains. TLBI domains (FEAT_TLBID) is > > an Arm architecture feature that enables a TLB invalidation to target a subset > > of CPUs instead of the whole system. It can improve performance on systems with > > many CPUs. TLBID is not yet part of the Arm Architecture Reference Manual but > > some of it is described in the latest XML [1]. > > > > The goal of this series is to send TLBI commands only to the CPUs where a > > process has run (i.e. where its page tables have been installed). The last > > IIUC, mm_cpumask() is used to store this information on x86 and other > archs. I see you put this information in tlbid_domains of mm_context_t > from patch 9, although in the form of tlb id domains. I wonder why not > make arm64 also update mm_cpumask() like x86 and other archs and derive > the tlbid domains based on mm_cpumask() and a cpu-to-domain mapping > (added in patch 7). One reason is that it's cheaper to compute the tlbi domains at context switch time (bitmap-and IIRC) than working from mm_cpumask() every time we do a TLBI. That said, suggestions for a quick algorithm are welcome. Subject to the race conditions Will mentioned, we could use the mm_cpumask() for a quick check if we ever ran on that CPU and avoid recomputing the tlbi domains. -- Catalin