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Sat, 27 Jul 2024 05:18:30 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-582-g5a02f8850-fm-20240719.002-g5a02f885 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: In-Reply-To: <7418bfcd-c572-4574-accc-7f2ae117529f@kernel.org> References: <20240726225910.1912537-1-romank@linux.microsoft.com> <20240726225910.1912537-7-romank@linux.microsoft.com> <7418bfcd-c572-4574-accc-7f2ae117529f@kernel.org> Date: Sat, 27 Jul 2024 11:17:20 +0200 From: "Arnd Bergmann" To: "Krzysztof Kozlowski" , "Roman Kisel" , bhelgaas@google.com, "Borislav Petkov" , "Catalin Marinas" , "Dave Hansen" , "Dexuan Cui" , "Haiyang Zhang" , "H. Peter Anvin" , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , "K. Y. Srinivasan" , "Len Brown" , "Lorenzo Pieralisi" , "Ingo Molnar" , "Rafael J . Wysocki" , "Rob Herring" , "Thomas Gleixner" , "Wei Liu" , "Will Deacon" , linux-acpi@vger.kernel.org, Linux-Arch , linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, x86@kernel.org Cc: apais@microsoft.com, benhill@microsoft.com, ssengar@microsoft.com, sunilmut@microsoft.com, vdso@hexbites.dev Subject: Re: [PATCH v3 6/7] Drivers: hv: vmbus: Get the IRQ number from DT Content-Type: text/plain On Sat, Jul 27, 2024, at 10:56, Krzysztof Kozlowski wrote: > On 27/07/2024 00:59, Roman Kisel wrote: >> @@ -2338,6 +2372,21 @@ static int vmbus_device_add(struct platform_device *pdev) >> cur_res = &res->sibling; >> } >> >> + /* >> + * Hyper-V always assumes DMA cache coherency, and the DMA subsystem >> + * might default to 'not coherent' on some architectures. >> + * Avoid high-cost cache coherency maintenance done by the CPU. >> + */ >> +#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ >> + defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ >> + defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) >> + >> + if (!of_property_read_bool(np, "dma-coherent")) >> + pr_warn("Assuming cache coherent DMA transactions, no 'dma-coherent' node supplied\n"); > > Why do you need this property at all, if it is allways dma-coherent? Are > you supporting dma-noncoherent somewhere? It's just a sanity check that the DT is well-formed. Since the dma-coherent property is interpreted by common code, it's not up to hv to change the default for the platform. I'm not sure if the presence of CONFIG_ARCH_HAS_SYNC_DMA_* options is the correct check to determine that an architecture defaults to noncoherent though, as the function may be needed to do something else. The global "dma_default_coherent' may be a better thing to check for. This is e.g. set on powerpc64, riscv and on specific mips platforms, but it's never set on arm64 as far as I can tell. Arnd