Re: Information regarding C3 cpu state and bus mastering activity

Janosch Machowinski
2005-12-12T12:47:39Z

Phillip Susi wrote:
> I'm kind of confused as to why this is a problem myself. Yes, the CPU
> cache does not snoop the busmaster activity and so the cache can become
> out of sync with ram, but isn't it the job of the driver that initiates
> the dma transfer to invalidate those cache lines once the transfer is
> complete to bring the cache back into sync?

Normally a cache should be completely hidden from the system, so a
driver can never determine the actually state of the cache. Only way to
sync the cache is to completely flush it.

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