From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E41A949620; Fri, 10 Oct 2025 16:53:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760115193; cv=none; b=Di2AzBPtyTD8ZcOWynk9BQMxNVgAELMZgzgN6zLmJbSY7cjiOxrUWZch4I8fQW/Wogt/fMkCr8y2QFUNrmVOrf0aP+8EPIl0DEHY3DHCQiBiYYAPL2Sa8dhQCGXUXbtm9e9Xh4lrPTK0i5jRX2xyf6ig1CtfDS3KPcMNjgn9HmE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760115193; c=relaxed/simple; bh=NvHno/MeFbr57dMbH3NV1tNKl1NOg7uNhF56N3nM4VE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=dXT0vhmmDWIc7YmRIq4CIEZVLIsRVOwFcgmON1lLYbk5BTjJxn55c5ZXmt0KJgQezcKPHOnKuyK3702i6mtjf9Yf1WFu9bS9aTiGxVQKy/KP+cbnANHLs5FuNN2ZDKDqva9ngxE1QaUOqmVeqpJisAb4Q6GeC8h65KIaQwrgFR4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1649153B; Fri, 10 Oct 2025 09:53:01 -0700 (PDT) Received: from [10.1.197.69] (eglon.cambridge.arm.com [10.1.197.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30B843F66E; Fri, 10 Oct 2025 09:53:04 -0700 (PDT) Message-ID: Date: Fri, 10 Oct 2025 17:53:02 +0100 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 26/29] arm_mpam: Use long MBWU counters if supported To: Jonathan Cameron Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan References: <20250910204309.20751-1-james.morse@arm.com> <20250910204309.20751-27-james.morse@arm.com> <20250912142929.00003cff@huawei.com> Content-Language: en-GB From: James Morse In-Reply-To: <20250912142929.00003cff@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Jonathan, On 12/09/2025 14:29, Jonathan Cameron wrote: > On Wed, 10 Sep 2025 20:43:06 +0000 > James Morse wrote: > >> From: Rohit Mathew >> >> If the 44 bit (long) or 63 bit (LWD) counters are detected on probing >> the RIS, use long/LWD counter instead of the regular 31 bit mbwu >> counter. >> >> Only 32bit accesses to the MSC are required to be supported by the >> spec, but these registers are 64bits. The lower half may overflow >> into the higher half between two 32bit reads. To avoid this, use >> a helper that reads the top half multiple times to check for overflow. >> >> Signed-off-by: Rohit Mathew >> [morse: merged multiple patches from Rohit] >> Signed-off-by: James Morse >> Reviewed-by: Ben Horgan > > Reviewed-by: Jonathan Cameron Thanks! Your push back on the 'front facing' thing in the previous patch made some knock on changes here, but I think they're minor. Thanks, James