From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hanjun Guo Subject: Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C Date: Tue, 6 Jun 2017 16:43:32 +0800 Message-ID: References: <11ef7d28c535c01d42b7b3c8e632934f0e0f1048.1495459319.git.robin.murphy@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pf0-f177.google.com ([209.85.192.177]:34180 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751184AbdFFInw (ORCPT ); Tue, 6 Jun 2017 04:43:52 -0400 Received: by mail-pf0-f177.google.com with SMTP id 9so95377158pfj.1 for ; Tue, 06 Jun 2017 01:43:51 -0700 (PDT) In-Reply-To: <11ef7d28c535c01d42b7b3c8e632934f0e0f1048.1495459319.git.robin.murphy@arm.com> Content-Language: en-US Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: Robin Murphy , will.deacon@arm.com, joro@8bytes.org Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, gakula@caviumnetworks.com, linu.cherian@cavium.com, rrichter@cavium.com, lorenzo.pieralisi@arm.com, john.garry@huawei.com, shameerali.kolothum.thodi@huawei.com, gabriele.paoloni@huawei.com, rjw@rjwysocki.net, robert.moore@intel.com, lv.zheng@intel.comShameerali Kolothum Thodi On 2017/5/22 23:06, Robin Murphy wrote: > IORT revision C has been published with a number of new SMMU > implementation identifiers. Since IORT doesn't have any way of falling > back to a more generic model code, we really need Linux to know about > these before vendors start updating their firmware tables to use them. > > CC: Rafael J. Wysocki > CC: Robert Moore > CC: Lv Zheng > Acked-by: Robert Richter > Tested-by: Robert Richter > Signed-off-by: Robin Murphy > --- > > v2: Update more comments, add Robert's tags. > > I'm including this here as a kernel patch just for context - once I've > figured out how we actually submit patches to ACPICA directly, I'll do > that per the preferred process. > > Robin. > > include/acpi/actbl2.h | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h > index faa9f2c0d5de..f469ea41f2fd 100644 > --- a/include/acpi/actbl2.h > +++ b/include/acpi/actbl2.h > @@ -663,7 +663,7 @@ struct acpi_ibft_target { > * IORT - IO Remapping Table > * > * Conforms to "IO Remapping Table System Software on ARM Platforms", > - * Document number: ARM DEN 0049B, October 2015 > + * Document number: ARM DEN 0049C, May 2017 > * > ******************************************************************************/ > > @@ -778,6 +778,8 @@ struct acpi_iort_smmu { > #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ > #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ > #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ > +#define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ > +#define ACPI_IORT_SMMU_CAVIUM_SMMUV2 0x00000005 /* Cavium ThunderX SMMUv2 */ > > /* Masks for Flags field above */ > > @@ -798,13 +800,19 @@ struct acpi_iort_smmu_v3 { > u32 flags; > u32 reserved; > u64 vatos_address; > - u32 model; /* O: generic SMMUv3 */ > + u32 model; > u32 event_gsiv; > u32 pri_gsiv; > u32 gerr_gsiv; > u32 sync_gsiv; > }; > > +/* Values for Model field above */ > + > +#define ACPI_IORT_SMMU_V3 0x00000000 /* Generic SMMUv3 */ > +#define ACPI_IORT_SMMU_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */ > +#define ACPI_IORT_SMMU_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ > + > /* Masks for Flags field above */ > > #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) > Looks good to me, Reviewed-by: Hanjun Guo By the way, how will this patch be merged? There are pending patches on top of it, Rafael suggested to work with ACPICA upstream first [1], Robin, will work on that? [1]: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1394295.html Thanks Hanjun