From: Samuel Holland <samuel.holland@sifive.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org
Cc: Anup Patel <apatel@ventanamicro.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Atish Kumar Patra <atishp@rivosinc.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Conor Dooley <conor.dooley@microchip.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Jones <ajones@ventanamicro.com>,
Ard Biesheuvel <ardb@kernel.org>, Len Brown <lenb@kernel.org>
Subject: Re: [PATCH v2 -next 3/4] RISC-V: cacheflush: Initialize CBO variables on ACPI systems
Date: Tue, 3 Oct 2023 14:50:02 -0500 [thread overview]
Message-ID: <f4ab7464-3dfb-4d10-8bed-76e7084abd3e@sifive.com> (raw)
In-Reply-To: <20230927170015.295232-4-sunilvl@ventanamicro.com>
On 2023-09-27 12:00 PM, Sunil V L wrote:
> Using new interface to get the CBO block size information in RHCT,
> initialize the variables on ACPI platforms.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++++------
> 1 file changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index f1387272a551..8e59644e473c 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -3,7 +3,9 @@
> * Copyright (C) 2017 SiFive
> */
>
> +#include <linux/acpi.h>
> #include <linux/of.h>
> +#include <asm/acpi.h>
> #include <asm/cacheflush.h>
>
> #ifdef CONFIG_SMP
> @@ -124,15 +126,38 @@ void __init riscv_init_cbo_blocksizes(void)
> unsigned long cbom_hartid, cboz_hartid;
> u32 cbom_block_size = 0, cboz_block_size = 0;
> struct device_node *node;
> + struct acpi_table_header *rhct;
> + acpi_status status;
> + unsigned int cpu;
> +
> + if (!acpi_disabled) {
> + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> + if (ACPI_FAILURE(status))
> + return;
> + }
>
> - for_each_of_cpu_node(node) {
> - /* set block-size for cbom and/or cboz extension if available */
> - cbo_get_block_size(node, "riscv,cbom-block-size",
> - &cbom_block_size, &cbom_hartid);
> - cbo_get_block_size(node, "riscv,cboz-block-size",
> - &cboz_block_size, &cboz_hartid);
> + for_each_possible_cpu(cpu) {
> + if (acpi_disabled) {
> + node = of_cpu_device_node_get(cpu);
> + if (!node) {
> + pr_warn("Unable to find cpu node\n");
> + continue;
> + }
> +
> + /* set block-size for cbom and/or cboz extension if available */
> + cbo_get_block_size(node, "riscv,cbom-block-size",
> + &cbom_block_size, &cbom_hartid);
> + cbo_get_block_size(node, "riscv,cboz-block-size",
> + &cboz_block_size, &cboz_hartid);
This leaks a reference to the device node.
> + } else {
> + acpi_get_cbo_block_size(rhct, cpu, &cbom_block_size,
> + &cboz_block_size, NULL);
This function loops through the whole RHCT already. Why do we need to call it
for each CPU? Can't we just call it once, and have it do the same consistency
checks as cbo_get_block_size()?
In that case, the DT path could keep the for_each_of_cpu_node() loop.
Regards,
Samuel
> + }
> }
>
> + if (!acpi_disabled && rhct)
> + acpi_put_table((struct acpi_table_header *)rhct);
> +
> if (cbom_block_size)
> riscv_cbom_block_size = cbom_block_size;
>
next prev parent reply other threads:[~2023-10-03 19:50 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 17:00 [PATCH v2 -next 0/4] RISC-V: ACPI improvements Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 1/4] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Sunil V L
2023-10-02 15:53 ` Conor Dooley
2023-10-03 18:53 ` Alexandre Ghiti
2023-10-04 10:33 ` Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 2/4] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 3/4] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Sunil V L
2023-10-02 15:50 ` Conor Dooley
2023-10-03 19:50 ` Samuel Holland [this message]
2023-10-04 4:22 ` Sunil V L
2023-10-04 8:33 ` Andrew Jones
2023-10-04 10:13 ` Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 4/4] clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu Sunil V L
2023-09-27 20:15 ` Samuel Holland
2023-10-02 15:46 ` Conor Dooley
2023-10-04 8:38 ` Andrew Jones
2023-10-11 9:14 ` Daniel Lezcano
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f4ab7464-3dfb-4d10-8bed-76e7084abd3e@sifive.com \
--to=samuel.holland@sifive.com \
--cc=ajones@ventanamicro.com \
--cc=alexghiti@rivosinc.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=aou@eecs.berkeley.edu \
--cc=apatel@ventanamicro.com \
--cc=ardb@kernel.org \
--cc=atishp@rivosinc.com \
--cc=conor.dooley@microchip.com \
--cc=daniel.lezcano@linaro.org \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=rafael@kernel.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox