From: "Verma, Vishal L" <vishal.l.verma@intel.com>
To: "rafael@kernel.org" <rafael@kernel.org>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"Jonathan.Cameron@huawei.com" <Jonathan.Cameron@huawei.com>,
"Williams, Dan J" <dan.j.williams@intel.com>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
"Moore, Robert" <robert.moore@intel.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"dave@stgolabs.net" <dave@stgolabs.net>
Subject: Re: [PATCH v4 3/3] PCI/ACPI: negotiate CXL _OSC
Date: Tue, 5 Apr 2022 15:55:47 +0000 [thread overview]
Message-ID: <f7ee304bacd05e2407bc98138efdd7f291c0aad3.camel@intel.com> (raw)
In-Reply-To: <CAJZ5v0haSXXDXaJdWEqpwS=b8r2HQzffKCoVpeDbxY9No5QXfw@mail.gmail.com>
On Tue, 2022-04-05 at 16:00 +0200, Rafael J. Wysocki wrote:
> On Thu, Mar 31, 2022 at 10:20 PM Vishal Verma <vishal.l.verma@intel.com> wrote:
> >
> > Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
> > applicable to CXL-enabled platforms. Advertise support for the CXL
> > features we support - 'CXL 2.0 port/device register access', 'Protocol
> > Error Reporting', and 'CXL Native Hot Plug'. Request control for 'CXL
> > Memory Error Reporting'. The requests are dependent on CONFIG_* based
> > prerequisites, and prior PCI enabling, similar to how the standard PCI
> > _OSC bits are determined.
> >
> > The CXL specification does not define any additional constraints on
> > the hotplug flow beyond PCIe native hotplug, so a kernel that supports
> > native PCIe hotplug, supports CXL hotplug. For error handling protocol
> > and link errors just use PCIe AER. There is nascent support for
> > amending AER events with CXL specific status [1], but there's
> > otherwise no additional OS responsibility for CXL errors beyond PCIe
> > AER. CXL Memory Errors behave the same as typical memory errors so
> > CONFIG_MEMORY_FAILURE is sufficient to indicate support to platform
> > firmware.
> >
> > [1]: https://lore.kernel.org/linux-cxl/164740402242.3912056.8303625392871313860.stgit@dwillia2-desk3.amr.corp.intel.com/
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> > Cc: Robert Moore <robert.moore@intel.com>
> > Cc: Dan Williams <dan.j.williams@intel.com>
> > Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
> > ---
> > include/linux/acpi.h | 28 +++++++-
> > include/acpi/acpi_bus.h | 6 +-
> > drivers/acpi/pci_root.c | 145 ++++++++++++++++++++++++++++++++++------
> > 3 files changed, 157 insertions(+), 22 deletions(-)
> >
> > diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> > index fc40da914315..cf360b9642d9 100644
> > --- a/include/linux/acpi.h
> > +++ b/include/linux/acpi.h
> > @@ -554,10 +554,15 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
> > #define OSC_PCI_CAPABILITY_DWORDS 3
> > #define OSC_CXL_CAPABILITY_DWORDS 5
> >
> > -/* Indexes into _OSC Capabilities Buffer (DWORDs 2 & 3 are device-specific) */
> > +/*
> > + * Indexes into _OSC Capabilities Buffer
> > + * DWORDs 2 & 3 are device-specific, and 4 & 5 are specific to CXL platforms
>
> Say "DWORDs 2 through 5 are device-specific" and you don't need to
> mention CXL here.
>
> > + */
> > #define OSC_QUERY_DWORD 0 /* DWORD 1 */
> > #define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
> > #define OSC_CONTROL_DWORD 2 /* DWORD 3 */
> > +#define OSC_CXL_SUPPORT_DWORD 3 /* DWORD 4 */
> > +#define OSC_CXL_CONTROL_DWORD 4 /* DWORD 5 */
>
> I would rename the last two symbols as OSC_EXT_SUPPORT_DWORD and
> OSC_EXT_CONTROL_DWORD (see below for an explanation).
>
>
Yep, dropping CXL references here and the 'extended' naming sounds
good, I'll update with these changes.
prev parent reply other threads:[~2022-04-05 20:48 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-31 20:20 [PATCH v4 0/3] PCI/ACPI: add support for CXL _OSC Vishal Verma
2022-03-31 20:20 ` [PATCH v4 1/3] PCI/ACPI: add a helper for retrieving _OSC Control DWORDs Vishal Verma
2022-04-05 13:39 ` Rafael J. Wysocki
2022-03-31 20:20 ` [PATCH v4 2/3] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
2022-04-05 13:47 ` Rafael J. Wysocki
2022-04-05 15:59 ` Verma, Vishal L
2022-03-31 20:20 ` [PATCH v4 3/3] PCI/ACPI: negotiate CXL _OSC Vishal Verma
2022-04-01 20:40 ` Davidlohr Bueso
2022-04-01 21:34 ` Dan Williams
2022-04-04 20:30 ` Davidlohr Bueso
2022-04-05 15:57 ` Verma, Vishal L
2022-04-05 14:00 ` Rafael J. Wysocki
2022-04-05 15:55 ` Verma, Vishal L [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f7ee304bacd05e2407bc98138efdd7f291c0aad3.camel@intel.com \
--to=vishal.l.verma@intel.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=dave@stgolabs.net \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=rafael.j.wysocki@intel.com \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox