From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: [PATCH-tip 15/22] locking/rwsem: Merge owner into count on x86-64 Date: Thu, 7 Feb 2019 21:08:48 +0100 Message-ID: <20190207200848.GH32477@hirez.programming.kicks-ass.net> References: <1549566446-27967-1-git-send-email-longman@redhat.com> <1549566446-27967-16-git-send-email-longman@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qdSlesKFFBxk29x974fyKv8bS3iQHPHQjG7Yeexpa4Q=; b=CfreIpBSULOb2S xfa/jLcpo7DhF3g/8SFr5WIH0a28kqU4jnL88uUS0GGKJjIug1Cx9V0TxIP2XmnFV/VLbslaxnqbu EySoO4vzLVWracuSSfgrHdLuzTY8XpWD2YCcxIezw1HJbDetbutSVIcGC8kbJ6R6uAUdZQMK7Ata0 zTxHywnx5pYyK+04SgIIc78elUUj/a8Qonw0R7n2eIu/RnKiyKJch3lSgCLpGBuv35V6iwWjBA4lf M1epq4Pr4mgTsLq8WS0HsBHqR6fCYY9o7YM68jlvQAu5CsicNkadqSBMMg2L3EpYFdUkjt7QfWa5x rkCdfvLwNsOopmKpWFIA==; Content-Disposition: inline In-Reply-To: <1549566446-27967-16-git-send-email-longman@redhat.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Waiman Long Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Davidlohr Bueso , linux-ia64@vger.kernel.org, Tim Chen , Arnd Bergmann , linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Linus Torvalds , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, Andrew Morton , linux-arm-kernel@lists.infradead.org On Thu, Feb 07, 2019 at 02:07:19PM -0500, Waiman Long wrote: > On 32-bit architectures, there aren't enough bits to hold both. > 64-bit architectures, however, can have enough bits to do that. For > x86-64, the physical address can use up to 52 bits. That is 4PB of > memory. That leaves 12 bits available for other use. The task structure > pointer is also aligned to the L1 cache size. That means another 6 bits > (64 bytes cacheline) will be available. Reserving 2 bits for status > flags, we will have 16 bits for the reader count. That can supports > up to (64k-1) readers. 64k readers sounds like a number that is fairly 'easy' to reach, esp. on 64bit. These are preemptible locks after all, all we need to do is get 64k tasks nested on enough CPUs. I'm sure there's some willing Java proglet around that spawns more than 64k threads just because it can. Run it on a big enough machine (ISTR there's a number of >1k CPU systems out there) and voila.