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[37.123.143.144]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5ad2e161e70sm788949e87.5.2026.06.12.13.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jun 2026 13:33:29 -0700 (PDT) From: Magnus Lindholm To: richard.henderson@linaro.org, mattst88@gmail.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Cc: glaubitz@physik.fu-berlin.de, mcree@orcon.net.nz, ink@unseen.parts, macro@orcam.me.uk, Magnus Lindholm Subject: [PATCH v3 6/8] alpha: use raw spinlocks for low-level platform locks Date: Fri, 12 Jun 2026 22:26:54 +0200 Message-ID: <20260612203006.2265557-7-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260612203006.2265557-1-linmag7@gmail.com> References: <20260612203006.2265557-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-alpha@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some Alpha platform locks are used as low-level hardware serialization locks in interrupt-controller and chipset access paths. These paths can run while IRQ state is being changed or while lockdep is tracking that state, so regular spinlock instrumentation is not appropriate once lockdep is enabled. Convert the affected Tsunami and Rawhide platform locks to raw_spinlock_t. This keeps the locks as simple hardware serialization locks and avoids lockdep recursion or IRQ-state mismatches when CONFIG_PROVE_LOCKING is enabled. This is a preparatory change for enabling lockdep hardirq state tracking on Alpha. Reviewed-by: Matt Turner Tested-by: Matt Turner Signed-off-by: Magnus Lindholm --- arch/alpha/kernel/irq_i8259.c | 19 +++++++++++------ arch/alpha/kernel/sys_dp264.c | 38 ++++++++++++++++++++++----------- arch/alpha/kernel/sys_rawhide.c | 17 +++++++++------ 3 files changed, 47 insertions(+), 27 deletions(-) diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index 29c6c477ac35..28f7b0680564 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c @@ -22,7 +22,7 @@ /* Note mask bit is true for DISABLED irqs. */ static unsigned int cached_irq_mask = 0xffff; -static DEFINE_SPINLOCK(i8259_irq_lock); +static DEFINE_RAW_SPINLOCK(i8259_irq_lock); static inline void i8259_update_irq_hw(unsigned int irq, unsigned long mask) @@ -36,9 +36,11 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask) inline void i8259a_enable_irq(struct irq_data *d) { - spin_lock(&i8259_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&i8259_irq_lock, flags); i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); - spin_unlock(&i8259_irq_lock); + raw_spin_unlock_irqrestore(&i8259_irq_lock, flags); } static inline void @@ -50,17 +52,20 @@ __i8259a_disable_irq(unsigned int irq) void i8259a_disable_irq(struct irq_data *d) { - spin_lock(&i8259_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&i8259_irq_lock, flags); __i8259a_disable_irq(d->irq); - spin_unlock(&i8259_irq_lock); + raw_spin_unlock_irqrestore(&i8259_irq_lock, flags); } void i8259a_mask_and_ack_irq(struct irq_data *d) { unsigned int irq = d->irq; + unsigned long flags; - spin_lock(&i8259_irq_lock); + raw_spin_lock_irqsave(&i8259_irq_lock, flags); __i8259a_disable_irq(irq); /* Ack the interrupt making it the lowest priority. */ @@ -69,7 +74,7 @@ i8259a_mask_and_ack_irq(struct irq_data *d) irq = 2; } outb(0xE0 | irq, 0x20); /* ack the master */ - spin_unlock(&i8259_irq_lock); + raw_spin_unlock_irqrestore(&i8259_irq_lock, flags); } struct irq_chip i8259a_irq_type = { diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 9fb445d7dca5..0a2d319bb1c8 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -41,7 +41,7 @@ static unsigned long cached_irq_mask; /* dp264 boards handle at max four CPUs */ static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; -DEFINE_SPINLOCK(dp264_irq_lock); +static DEFINE_RAW_SPINLOCK(dp264_irq_lock); static void tsunami_update_irq_hw(unsigned long mask) @@ -99,37 +99,45 @@ tsunami_update_irq_hw(unsigned long mask) static void dp264_enable_irq(struct irq_data *d) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cached_irq_mask |= 1UL << d->irq; tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); } static void dp264_disable_irq(struct irq_data *d) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cached_irq_mask &= ~(1UL << d->irq); tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); } static void clipper_enable_irq(struct irq_data *d) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cached_irq_mask |= 1UL << (d->irq - 16); tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); } static void clipper_disable_irq(struct irq_data *d) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cached_irq_mask &= ~(1UL << (d->irq - 16)); tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); } static void @@ -151,10 +159,12 @@ static int dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cpu_set_irq_affinity(d->irq, *affinity); tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); return 0; } @@ -163,10 +173,12 @@ static int clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { - spin_lock(&dp264_irq_lock); + unsigned long flags; + + raw_spin_lock_irqsave(&dp264_irq_lock, flags); cpu_set_irq_affinity(d->irq - 16, *affinity); tsunami_update_irq_hw(cached_irq_mask); - spin_unlock(&dp264_irq_lock); + raw_spin_unlock_irqrestore(&dp264_irq_lock, flags); return 0; } diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index b5846ffdadce..b4a08890dce9 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c @@ -41,7 +41,7 @@ static unsigned int hose_irq_masks[4] = { 0xff0000, 0xfe0000, 0xff0000, 0xff0000 }; static unsigned int cached_irq_masks[4]; -DEFINE_SPINLOCK(rawhide_irq_lock); +DEFINE_RAW_SPINLOCK(rawhide_irq_lock); static inline void rawhide_update_irq_hw(int hose, int mask) @@ -59,6 +59,7 @@ rawhide_enable_irq(struct irq_data *d) { unsigned int mask, hose; unsigned int irq = d->irq; + unsigned long flags; irq -= 16; hose = irq / 24; @@ -68,11 +69,11 @@ rawhide_enable_irq(struct irq_data *d) irq -= hose * 24; mask = 1 << irq; - spin_lock(&rawhide_irq_lock); + raw_spin_lock_irqsave(&rawhide_irq_lock, flags); mask |= cached_irq_masks[hose]; cached_irq_masks[hose] = mask; rawhide_update_irq_hw(hose, mask); - spin_unlock(&rawhide_irq_lock); + raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); } static void @@ -80,6 +81,7 @@ rawhide_disable_irq(struct irq_data *d) { unsigned int mask, hose; unsigned int irq = d->irq; + unsigned long flags; irq -= 16; hose = irq / 24; @@ -89,11 +91,11 @@ rawhide_disable_irq(struct irq_data *d) irq -= hose * 24; mask = ~(1 << irq) | hose_irq_masks[hose]; - spin_lock(&rawhide_irq_lock); + raw_spin_lock_irqsave(&rawhide_irq_lock, flags); mask &= cached_irq_masks[hose]; cached_irq_masks[hose] = mask; rawhide_update_irq_hw(hose, mask); - spin_unlock(&rawhide_irq_lock); + raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); } static void @@ -101,6 +103,7 @@ rawhide_mask_and_ack_irq(struct irq_data *d) { unsigned int mask, mask1, hose; unsigned int irq = d->irq; + unsigned long flags; irq -= 16; hose = irq / 24; @@ -111,7 +114,7 @@ rawhide_mask_and_ack_irq(struct irq_data *d) mask1 = 1 << irq; mask = ~mask1 | hose_irq_masks[hose]; - spin_lock(&rawhide_irq_lock); + raw_spin_lock_irqsave(&rawhide_irq_lock, flags); mask &= cached_irq_masks[hose]; cached_irq_masks[hose] = mask; @@ -120,7 +123,7 @@ rawhide_mask_and_ack_irq(struct irq_data *d) /* Clear the interrupt. */ *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; - spin_unlock(&rawhide_irq_lock); + raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); } static struct irq_chip rawhide_irq_type = { -- 2.53.0