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Thu, 29 Oct 2026 21:04:11 -0700 (PDT) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67ba7514e84sm310708d50.16.2026.10.29.21.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 21:04:10 -0700 (PDT) From: Matt Turner Date: Fri, 30 Oct 2026 00:04:03 -0400 Subject: [PATCH v2 5/5] alpha/perf: optionally randomize the ProfileMe sampling interval X-Mailing-List: linux-alpha@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261030-alpha-profileme-v2-5-c702f1c65272@gmail.com> References: <20261030-alpha-profileme-v2-0-c702f1c65272@gmail.com> In-Reply-To: <20261030-alpha-profileme-v2-0-c702f1c65272@gmail.com> To: Richard Henderson , Magnus Lindholm , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4423; i=mattst88@gmail.com; h=from:subject:message-id; bh=k1TKL1tsmpw+6SouF+Nkc9CqghjK65hgxaoQW1zZB34=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLKeiOv3sUVzTfoceWLxFj7mw8c2O780YnxbnHfx1vLXP 4/nnJizueMjC4MYF8NMMUWWuPWKLLPadiz1OS39C2YOKxPIEGmRBgYgYGHgy03MKzXSMdIz1TbU MwQydIziIXJ6DBqZxcWlqUW6aQVFDnn5JYklmfl5xXr5Bal5BekFemmZaSUZGflFxalAI/TyUkt MXR3djAwNTCwdLcycLBxNTZydnQyd3BwdnV2djCzNTQycLR1NXC3NGbg4BWCuWb+XkWF904sfLH 98r1VPTV5zSPmC4P3SJ+I5utVVFw7p8Xbf36PC8D+zsLjPOlX49y2DXTsE9A+cObD+TtXxO1ebV 24pPX8zcxsHAA== X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A A fixed sampling interval can phase-lock with a loop whose length divides it, so that the same few instructions are profiled over and over while the rest of the loop is never seen. DCPI avoided this by randomizing the interval. Add a randomize config bit that varies each interval by up to 1/16 of the period in either direction. Only ProfileMe events accept it, since Aggregate mode samples already land a variable distance from the instruction that overflowed. Counts are unaffected, because prev_count already records the value actually written to the counter. The jitter is computed with mul_u64_u32_shr() and the sum saturates, so that a period beyond 32 bits cannot overflow. The jitter comes from a per-CPU prandom state rather than get_random_u32_below(), which takes the batched entropy local lock and triggers an invalid wait context report from lockdep in the PMI. Signed-off-by: Matt Turner --- arch/alpha/kernel/perf_event.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index c9d4b13817bc..c553cbd6c7a3 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -16,6 +16,9 @@ #include #include #include +#include +#include +#include #include #include @@ -33,9 +36,11 @@ /* Layout of attr.config for PERF_TYPE_RAW events; see format/ in sysfs. */ #define ALPHA_PERF_CONFIG_EVENT 0xffULL #define ALPHA_PERF_CONFIG_PROFILEME BIT_ULL(8) +#define ALPHA_PERF_CONFIG_RANDOMIZE BIT_ULL(9) /* hw_perf_event.flags */ #define ALPHA_PERF_FLAG_PROFILEME 0x1 +#define ALPHA_PERF_FLAG_RANDOMIZE 0x2 /* For tracking PMCs and the hw events they monitor on each CPU. */ struct cpu_hw_events { @@ -59,6 +64,9 @@ struct cpu_hw_events { }; DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); +/* For randomizing sample intervals from the PMI, where locks are not allowed. */ +static DEFINE_PER_CPU(struct rnd_state, alpha_perf_rnd); + /* @@ -246,10 +254,12 @@ static int ev67_raw_event_valid(u64 config) PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(profileme, "config:8"); +PMU_FORMAT_ATTR(randomize, "config:9"); static struct attribute *ev67_format_attrs[] = { &format_attr_event.attr, &format_attr_profileme.attr, + &format_attr_randomize.attr, NULL, }; @@ -367,6 +377,22 @@ static int alpha_perf_event_set_period(struct perf_event *event, ret = 1; } + /* + * Vary each new interval by up to 1/16 of the period either way, so + * the samples cannot phase-lock with a loop whose length divides the + * period. The count stays exact because prev_count records the value + * actually written. + */ + if (ret && (hwc->flags & ALPHA_PERF_FLAG_RANDOMIZE) && period >= 8) { + long jitter = period / 8; + u32 r = prandom_u32_state(this_cpu_ptr(&alpha_perf_rnd)); + long offset = mul_u64_u32_shr(jitter, r, 32) - jitter / 2; + + if (check_add_overflow(left, offset, &left)) + left = LONG_MAX; + local64_set(&hwc->period_left, left); + } + /* * Hardware restrictions require that the counters must not be * written with values that are too close to the maximum period. @@ -738,7 +764,8 @@ static int __hw_perf_event_init(struct perf_event *event) return -EOPNOTSUPP; } else if (attr->type == PERF_TYPE_RAW) { if (attr->config & ~(ALPHA_PERF_CONFIG_EVENT | - ALPHA_PERF_CONFIG_PROFILEME)) + ALPHA_PERF_CONFIG_PROFILEME | + ALPHA_PERF_CONFIG_RANDOMIZE)) return -EINVAL; ev = attr->config & ALPHA_PERF_CONFIG_EVENT; if (!alpha_pmu->raw_event_valid(ev)) @@ -763,6 +790,14 @@ static int __hw_perf_event_init(struct perf_event *event) return -EINVAL; hwc->flags = profileme ? ALPHA_PERF_FLAG_PROFILEME : 0; + if (attr->type == PERF_TYPE_RAW && + (attr->config & ALPHA_PERF_CONFIG_RANDOMIZE)) { + if (!profileme) + return -EINVAL; + prandom_init_once(&alpha_perf_rnd); + hwc->flags |= ALPHA_PERF_FLAG_RANDOMIZE; + } + /* * We place the event type in event_base here and leave calculation * of the codes to programme the PMU for alpha_pmu_enable() because -- 2.55.0