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Fri, 11 Sep 2020 10:29:30 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CF67310002A; Fri, 11 Sep 2020 10:29:27 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BA60321E26A; Fri, 11 Sep 2020 10:29:27 +0200 (CEST) Received: from SFHDAG6NODE3.st.com (10.75.127.18) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 11 Sep 2020 10:29:27 +0200 Received: from SFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6]) by SFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6%20]) with mapi id 15.00.1473.003; Fri, 11 Sep 2020 10:29:27 +0200 From: Philippe CORNU To: Neil Armstrong , "a.hajda@samsung.com" , "Laurent.pinchart@ideasonboard.com" , "jonas@kwiboo.se" , "jernej.skrabec@siol.net" Subject: Re: [PATCH] drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate Thread-Topic: [PATCH] drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate Thread-Index: AQHWgrq0GnmfCHcy9EO3+U4LDjE6p6ljBFQA Date: Fri, 11 Sep 2020 08:29:27 +0000 Message-ID: <078aae69-936f-cb78-623f-6bdcb1c2630d@st.com> References: <20200904125531.15248-1-narmstrong@baylibre.com> In-Reply-To: <20200904125531.15248-1-narmstrong@baylibre.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] Content-ID: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-11_02:2020-09-10, 2020-09-11 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_042940_329797_45BCB512 X-CRM114-Status: GOOD ( 28.78 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yannick FERTRE , "heiko.stuebner@theobroma-systems.com" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On 9/4/20 2:55 PM, Neil Armstrong wrote: > The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency > higher than 10MHz for the TX Escape Clock, thus make the target rate > configurable. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++---- > include/drm/bridge/dw_mipi_dsi.h | 1 + > 2 files changed, 21 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > index d580b2aa4ce9..31fc965c66fd 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > @@ -562,15 +562,30 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) > > static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > { > + const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; > + unsigned int esc_rate; /* in MHz */ > + u32 esc_clk_division; > + int ret; > + > /* > * The maximum permitted escape clock is 20MHz and it is derived from > - * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: > - * > - * (lane_mbps >> 3) / esc_clk_division < 20 > + * lanebyteclk, which is running at "lane_mbps / 8". > + */ > + if (phy_ops->get_esc_clk_rate) { > + ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, > + &esc_rate); > + if (ret) > + DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); > + } else > + esc_rate = 20; /* Default to 20MHz */ > + > + /* > + * We want : > + * (lane_mbps >> 3) / esc_clk_division < X > * which is: > - * (lane_mbps >> 3) / 20 > esc_clk_division > + * (lane_mbps >> 3) / X > esc_clk_division > */ > - u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; > + esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; > > dsi_write(dsi, DSI_PWR_UP, RESET); > > diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h > index b0e390b3288e..bda8aa7c2280 100644 > --- a/include/drm/bridge/dw_mipi_dsi.h > +++ b/include/drm/bridge/dw_mipi_dsi.h > @@ -36,6 +36,7 @@ struct dw_mipi_dsi_phy_ops { > unsigned int *lane_mbps); > int (*get_timing)(void *priv_data, unsigned int lane_mbps, > struct dw_mipi_dsi_dphy_timing *timing); > + int (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate); > }; > > struct dw_mipi_dsi_host_ops { > Hi Neil, Thank you for the patch Reviewed-by: Philippe Cornu Philippe :-) _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic