USB PHY documentation

USB PHY documentation

[Martin Blumenstingl]

Hello,

last weekend I tried getting the USB PHY working on my GXBB device.
The simple part: resetting the USB part and enabling the clocks.
The tricky part: configuring the USB PHY registers

Unfortunately the public datasheet does not contain any information
about the USB PHY.
The reference driver does not contain many comments, the struct
members are using abbreviated names and it seems that a part of what
should be done by the PHY driver is part of the dwc driver
(usb_peri_reg changes were patched into it).
I am now wondering if someone can share some details from the datasheet.

I took my register #defines from the reference driver (and tried to
make them human readable): [0]
There are some USB_PHY_CLK_SEL_* definitions at the bottom which seem
interesting (at least for configuring REG_CONFIG_CLK_SEL, but
unfortunately I don't know if these are valid (for either meson8b or
gxbb)..

Symptoms are: dwc2's USB initialization is successful, but when I plug
in a device it's not being detected.
I *think* that my problem is that REG_ADP_BC_DRV_VBUS is a readonly
bit - it's set when I use the original firmware of my device, but I
cannot set it in my PHY driver.

In case anyone is interested how my changes look exactly, you can find
the code here: [1]

I also dumped the USB PHY registers from the original Android firmware
of my device in case anyone is interested:
phy0:
[0xc0000000] = 0x8000
[0xc0000004] = 0x1690500
[0xc0000008] = 0x0
[0xc000000c] = 0x8E18
[0xc0000010] = 0x0
[0xc0000014] = 0x80000
[0xc0000018] = 0x246613D
[0xc000001c] = 0x0

phy1:
[0xc0000020] = 0x8000
[0xc0000024] = 0x1690500
[0xc0000028] = 0x0
[0xc000002c] = 0x2010118
[0xc0000030] = 0x0
[0xc0000034] = 0x80000
[0xc0000038] = 0xE46613D
[0xc000003c] = 0x0

@Ben: did you get anywhere with your experiments on Meson8b (S805)?


Regards,
Martin


[0] https://github.com/150balbes/Amlogic_s905-kernel/blob/master/include/linux/amlogic/usb-meson8.h
[1] https://github.com/xdarklight/linux/commit/a1666af7fdb48734784fa368d568fd4209c5b125

USB PHY documentation

[Ben Dooks]

On 22/08/2016 22:39, Martin Blumenstingl wrote:
> Hello,
>
> last weekend I tried getting the USB PHY working on my GXBB device.
> The simple part: resetting the USB part and enabling the clocks.
> The tricky part: configuring the USB PHY registers
>
> Unfortunately the public datasheet does not contain any information
> about the USB PHY.
> The reference driver does not contain many comments, the struct
> members are using abbreviated names and it seems that a part of what
> should be done by the PHY driver is part of the dwc driver
> (usb_peri_reg changes were patched into it).
> I am now wondering if someone can share some details from the 
> datasheet.
>
> I took my register #defines from the reference driver (and tried to
> make them human readable): [0]
> There are some USB_PHY_CLK_SEL_* definitions at the bottom which seem
> interesting (at least for configuring REG_CONFIG_CLK_SEL, but
> unfortunately I don't know if these are valid (for either meson8b or
> gxbb)..
>
> Symptoms are: dwc2's USB initialization is successful, but when I 
> plug
> in a device it's not being detected.
> I *think* that my problem is that REG_ADP_BC_DRV_VBUS is a readonly
> bit - it's set when I use the original firmware of my device, but I
> cannot set it in my PHY driver.
>
> In case anyone is interested how my changes look exactly, you can 
> find
> the code here: [1]
>
> I also dumped the USB PHY registers from the original Android 
> firmware
> of my device in case anyone is interested:
> phy0:
> [0xc0000000] = 0x8000
> [0xc0000004] = 0x1690500
> [0xc0000008] = 0x0
> [0xc000000c] = 0x8E18
> [0xc0000010] = 0x0
> [0xc0000014] = 0x80000
> [0xc0000018] = 0x246613D
> [0xc000001c] = 0x0
>
> phy1:
> [0xc0000020] = 0x8000
> [0xc0000024] = 0x1690500
> [0xc0000028] = 0x0
> [0xc000002c] = 0x2010118
> [0xc0000030] = 0x0
> [0xc0000034] = 0x80000
> [0xc0000038] = 0xE46613D
> [0xc000003c] = 0x0
>
> @Ben: did you get anywhere with your experiments on Meson8b (S805)?

I did a PHY driver and some updates to the dwc2 driver, but could
not get a reliable USB session going. I'll post my PHY driver later
as it's still in bits and needs to be made into a semi-coherent patch
set.


-- 
Ben Dooks, Senior Engineer
http://www.codethink.co.uk/

USB PHY documentation

[jbrunet]

On Tue, 2016-08-23 at 14:30 +0100, Ben Dooks wrote:
> On 22/08/2016 22:39, Martin Blumenstingl wrote:
> > 
> > Hello,
> > 
> > last weekend I tried getting the USB PHY working on my GXBB device.
> > The simple part: resetting the USB part and enabling the clocks.
> > The tricky part: configuring the USB PHY registers
> > 
> > Unfortunately the public datasheet does not contain any information
> > about the USB PHY.
> > The reference driver does not contain many comments, the struct
> > members are using abbreviated names and it seems that a part of
> > what
> > should be done by the PHY driver is part of the dwc driver
> > (usb_peri_reg changes were patched into it).
> > I am now wondering if someone can share some details from the?
> > datasheet.
> > 
> > I took my register #defines from the reference driver (and tried to
> > make them human readable): [0]
> > There are some USB_PHY_CLK_SEL_* definitions at the bottom which
> > seem
> > interesting (at least for configuring REG_CONFIG_CLK_SEL, but
> > unfortunately I don't know if these are valid (for either meson8b
> > or
> > gxbb)..
> > 
> > Symptoms are: dwc2's USB initialization is successful, but when I?
> > plug
> > in a device it's not being detected.
> > I *think* that my problem is that REG_ADP_BC_DRV_VBUS is a readonly
> > bit - it's set when I use the original firmware of my device, but I
> > cannot set it in my PHY driver.
> > 
> > In case anyone is interested how my changes look exactly, you can?
> > find
> > the code here: [1]
> > 
> > I also dumped the USB PHY registers from the original Android?
> > firmware
> > of my device in case anyone is interested:
> > phy0:
> > [0xc0000000] = 0x8000
> > [0xc0000004] = 0x1690500
> > [0xc0000008] = 0x0
> > [0xc000000c] = 0x8E18
> > [0xc0000010] = 0x0
> > [0xc0000014] = 0x80000
> > [0xc0000018] = 0x246613D
> > [0xc000001c] = 0x0
> > 
> > phy1:
> > [0xc0000020] = 0x8000
> > [0xc0000024] = 0x1690500
> > [0xc0000028] = 0x0
> > [0xc000002c] = 0x2010118
> > [0xc0000030] = 0x0
> > [0xc0000034] = 0x80000
> > [0xc0000038] = 0xE46613D
> > [0xc000003c] = 0x0
> > 
> > @Ben: did you get anywhere with your experiments on Meson8b (S805)?
> 
> I did a PHY driver and some updates to the dwc2 driver, but could
> not get a reliable USB session going. I'll post my PHY driver later
> as it's still in bits and needs to be made into a semi-coherent patch
> set.
> 
> 
@Martin: I tried your patch and just done a few corrections, mainly
interrupt numbers in the device tree and otg_cap in amlogic_params in
dwc2 driver. the code is here [2]

The host controller seems to be working well on the p200, I'm still
checking the otg controller.

Regards
Jerome

[2]: https://github.com/jeromebrunet/linux/commits/amlogic/v4.8/usb

USB PHY documentation

[Martin Blumenstingl]

Hi Jerome,

On Wed, Aug 24, 2016 at 11:03 AM, jbrunet <jbrunet@baylibre.com> wrote:
>> > In case anyone is interested how my changes look exactly, you can
>> > find
>> > the code here: [1]
> @Martin: I tried your patch and just done a few corrections, mainly
> interrupt numbers in the device tree and otg_cap in amlogic_params in
> dwc2 driver. the code is here [2]
>
> The host controller seems to be working well on the p200, I'm still
> checking the otg controller.
oh, interrupt numbering is different in the reference kernel! Many
thanks for testing and figuring this out!

I can continue working on this on Friday / Saturday.
But if you want to go ahead and finish the patches: feel free to do so.

USB PHY documentation

[Martin Blumenstingl]

On Wed, Aug 24, 2016 at 11:03 AM, jbrunet <jbrunet@baylibre.com> wrote:
> I'm still checking the otg controller.
I've seen that you made more changes in your github repo.
Maybe you could give me/us an update before your leave today so I can
continue where you left tonight/tomorrow.

How should we proceed with signed-off-by in these patches?
We have both written/changed a part of it, should we both simply add
our own SOB to the patches?

USB PHY documentation

[Martin Blumenstingl]

On Fri, Aug 26, 2016 at 12:55 PM, J?r?me Brunet <jbrunet@baylibre.com> wrote:
> I did some test on the otg controller. I had to remove the reset in the PHY
> because it was reseting both of them, so the reset intended for the 2nd PHY
> was breaking the configuration of the 1st.
I am getting the following error when 1) removing the reset and 2)
booting the mainline kernel directly (without booting the stock
Android kernel first):
[    1.297507] dwc2 c9000000.usb-controller: dwc2_core_reset() HANG!
AHB Idle GRSTCTL=0
[    1.305116] dwc2 c9000000.usb-controller: Bad value for GSNPSID: 0x00000000

USB PHY documentation

[Martin Blumenstingl]

On Sat, Aug 27, 2016 at 11:32 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> On Fri, Aug 26, 2016 at 12:55 PM, J?r?me Brunet <jbrunet@baylibre.com> wrote:
>> I did some test on the otg controller. I had to remove the reset in the PHY
>> because it was reseting both of them, so the reset intended for the 2nd PHY
>> was breaking the configuration of the 1st.
> I am getting the following error when 1) removing the reset and 2)
> booting the mainline kernel directly (without booting the stock
> Android kernel first):
> [    1.297507] dwc2 c9000000.usb-controller: dwc2_core_reset() HANG!
> AHB Idle GRSTCTL=0
> [    1.305116] dwc2 c9000000.usb-controller: Bad value for GSNPSID: 0x00000000
I added the reset back along with some code that ensures it only calls
the reset once.
That made the error go away on my board.

Additionally I forced the first USB controller to "host" mode (which
was also not working without the reset) due to the OTG problems you
have mentioned.
I did some basic tests with both USB controllers - everything looks good!
While doing that I found out that quite a lot bits in REG_ADP_BC are
readonly - one of them is REG_ADP_BC_DRV_VBUS so I removed the code
which set that bit.

Finally I added our signed-off-by's to the patches and improved the
patch subjects and descriptions.
You can find my updated tree here: [0] (or if you only care about the
USB patches: [1])

PS: I will only have limited access to my S905 device in the next two weeks.
Feel free to submit the patches once you think they are ready - having
USB (host) support in 4.9 would be awesome!


Regards,
Martin


[0] https://github.com/xdarklight/linux/commits/meson-gxbb-integration-4.8-20160827
[1] https://github.com/torvalds/linux/compare/0ff577bf040b312301920f8589fc9fcea84a86b8...6aebadf13dcfb631399e7717c5eec0e80d72c9a7