From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
Date: Thu, 19 Jul 2018 10:59:05 +0200 [thread overview]
Message-ID: <1531990745.26720.34.camel@baylibre.com> (raw)
In-Reply-To: <d4e5e35a-39e0-fe27-8d27-387c5312ca32@baylibre.com>
On Thu, 2018-07-19 at 10:44 +0200, Neil Armstrong wrote:
> We could even add ranges instead of table when we know the PLL supports a well-known continuous dividers range.
I was thinking about this too.
I did not went for it because it would mean yet another rework of the pll
driver, which I did not had time to do now.
I suspect that the min and max value of 'm' the pll can lock on might depend on
the input rate of the DCO, so past the 'n' prediv.
So, to replace the tuple (m, n) table with ranges, I think it would be best to
take the predivider 'n' out first and try to clarify the contraints on the input
rate of the DCO with amlogic ... we can also try and see ;)
>
> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
next prev parent reply other threads:[~2018-07-19 8:59 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 9:56 [PATCH 0/3] clk: meson: clk-pll driver update Jerome Brunet
2018-07-17 9:56 ` [PATCH 1/3] clk: meson: clk-pll: add enable bit Jerome Brunet
2018-07-19 8:33 ` Neil Armstrong
2018-07-21 19:48 ` Martin Blumenstingl
2018-07-21 20:26 ` Jerome Brunet
2018-07-17 9:56 ` [PATCH 2/3] clk: meson: clk-pll: remove od parameters Jerome Brunet
2018-07-19 8:42 ` Neil Armstrong
2018-07-19 8:45 ` Jerome Brunet
2018-07-21 20:01 ` Martin Blumenstingl
2018-07-21 20:42 ` Jerome Brunet
2018-07-21 21:37 ` Martin Blumenstingl
2018-07-17 9:56 ` [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables Jerome Brunet
2018-07-19 8:44 ` Neil Armstrong
2018-07-19 8:59 ` Jerome Brunet [this message]
2018-07-21 20:16 ` Martin Blumenstingl
2018-07-21 20:46 ` Jerome Brunet
2018-07-21 21:34 ` Martin Blumenstingl
2018-07-26 8:48 ` jbrunet at baylibre.com
2018-07-21 20:17 ` [PATCH 0/3] clk: meson: clk-pll driver update Martin Blumenstingl
2018-07-21 20:48 ` Jerome Brunet
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