* [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD
@ 2018-07-21 17:25 Martin Blumenstingl
2018-07-21 17:25 ` [PATCH 1/2] dt-bindings: clock: meson8b: export the CPU_DIV16 clock Martin Blumenstingl
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Martin Blumenstingl @ 2018-07-21 17:25 UTC (permalink / raw)
To: linus-amlogic
Carlo sent a .dts patch for the ARM TWD (timer watchdog) a long time
ago: [0]
This patch was never applied. While resurrecting it I found out (by
trial and error) that the TWD clock is derived from the CPU clock by
dividing the existing CPU clock by 16.
An additional hint was also given by Neil's clock measurer patch [1]
as the GX SoCs explicitly define a "sys_cpu_div16" clock with ID 18,
however old u-boot seems to call that CTS_LED_PLL_CLK. The rate of
this clock also matches CPU clock divided by 16 on my boards.
It's not clear if there is an additional gate for this clock. If there
is then it's not documented anywhere.
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/391928.html
[1] https://patchwork.kernel.org/patch/10504083/
Martin Blumenstingl (2):
dt-bindings: clock: meson8b: export the CPU_DIV16 clock
clk: meson: meson8b: add the CPU_DIV16 clock
drivers/clk/meson/meson8b.c | 12 ++++++++++++
drivers/clk/meson/meson8b.h | 2 +-
include/dt-bindings/clock/meson8b-clkc.h | 1 +
3 files changed, 14 insertions(+), 1 deletion(-)
--
2.18.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] dt-bindings: clock: meson8b: export the CPU_DIV16 clock
2018-07-21 17:25 [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Martin Blumenstingl
@ 2018-07-21 17:25 ` Martin Blumenstingl
2018-07-21 17:25 ` [PATCH 2/2] clk: meson: meson8b: add " Martin Blumenstingl
2018-07-23 9:11 ` [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Jerome Brunet
2 siblings, 0 replies; 6+ messages in thread
From: Martin Blumenstingl @ 2018-07-21 17:25 UTC (permalink / raw)
To: linus-amlogic
The CPU_DIV16 clock is used for the TWD timer on Meson8, Meson8b and
Meson8m2.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
include/dt-bindings/clock/meson8b-clkc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index a60f47b49231..041560d9a67b 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -103,5 +103,6 @@
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
+#define CLKID_CPU_DIV16 113
#endif /* __MESON8B_CLKC_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: meson: meson8b: add the CPU_DIV16 clock
2018-07-21 17:25 [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Martin Blumenstingl
2018-07-21 17:25 ` [PATCH 1/2] dt-bindings: clock: meson8b: export the CPU_DIV16 clock Martin Blumenstingl
@ 2018-07-21 17:25 ` Martin Blumenstingl
2018-07-23 9:11 ` [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Jerome Brunet
2 siblings, 0 replies; 6+ messages in thread
From: Martin Blumenstingl @ 2018-07-21 17:25 UTC (permalink / raw)
To: linus-amlogic
The TWD (timer and watchdog) of the Cortex-A9 (on Meson8 and Meson8m2)
and Cortex-A9 (on Meson8b) cores is clocked by the CPU clock divided by
16. Add this new clock so the TWD timer can be added.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 12 ++++++++++++
drivers/clk/meson/meson8b.h | 2 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 7447d96a265f..17f56f600e09 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -633,6 +633,17 @@ static struct clk_regmap meson8b_cpu_clk = {
},
};
+static struct clk_fixed_factor meson8b_cpu_div16_div = {
+ .mult = 1,
+ .div = 16,
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu_div16_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "cpu_clk" },
+ .num_parents = 1,
+ },
+};
+
static struct clk_regmap meson8b_nand_clk_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_NAND_CLK_CNTL,
@@ -879,6 +890,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_CPU_DIV16] = &meson8b_cpu_div16_div.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5d09412b5084..d790991d5055 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -76,7 +76,7 @@
#define CLKID_NAND_SEL 110
#define CLKID_NAND_DIV 111
-#define CLK_NR_CLKS 113
+#define CLK_NR_CLKS 114
/*
* include the CLKID and RESETID that have
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD
2018-07-21 17:25 [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Martin Blumenstingl
2018-07-21 17:25 ` [PATCH 1/2] dt-bindings: clock: meson8b: export the CPU_DIV16 clock Martin Blumenstingl
2018-07-21 17:25 ` [PATCH 2/2] clk: meson: meson8b: add " Martin Blumenstingl
@ 2018-07-23 9:11 ` Jerome Brunet
2018-09-26 9:56 ` Martin Blumenstingl
2 siblings, 1 reply; 6+ messages in thread
From: Jerome Brunet @ 2018-07-23 9:11 UTC (permalink / raw)
To: linus-amlogic
On Sat, 2018-07-21 at 19:25 +0200, Martin Blumenstingl wrote:
> Carlo sent a .dts patch for the ARM TWD (timer watchdog) a long time
> ago: [0]
> This patch was never applied. While resurrecting it I found out (by
> trial and error) that the TWD clock is derived from the CPU clock by
> dividing the existing CPU clock by 16.
> An additional hint was also given by Neil's clock measurer patch [1]
> as the GX SoCs explicitly define a "sys_cpu_div16" clock with ID 18,
> however old u-boot seems to call that CTS_LED_PLL_CLK. The rate of
> this clock also matches CPU clock divided by 16 on my boards.
>
> It's not clear if there is an additional gate for this clock. If there
> is then it's not documented anywhere.
>
>
> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/391928.html
> [1] https://patchwork.kernel.org/patch/10504083/
>
> Martin Blumenstingl (2):
> dt-bindings: clock: meson8b: export the CPU_DIV16 clock
> clk: meson: meson8b: add the CPU_DIV16 clock
>
> drivers/clk/meson/meson8b.c | 12 ++++++++++++
> drivers/clk/meson/meson8b.h | 2 +-
> include/dt-bindings/clock/meson8b-clkc.h | 1 +
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
Queued for 4.20
Thx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD
2018-07-23 9:11 ` [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Jerome Brunet
@ 2018-09-26 9:56 ` Martin Blumenstingl
2018-09-26 9:59 ` Jerome Brunet
0 siblings, 1 reply; 6+ messages in thread
From: Martin Blumenstingl @ 2018-09-26 9:56 UTC (permalink / raw)
To: linus-amlogic
Hi Jerome,
On Mon, Jul 23, 2018 at 11:11 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Sat, 2018-07-21 at 19:25 +0200, Martin Blumenstingl wrote:
> > Carlo sent a .dts patch for the ARM TWD (timer watchdog) a long time
> > ago: [0]
> > This patch was never applied. While resurrecting it I found out (by
> > trial and error) that the TWD clock is derived from the CPU clock by
> > dividing the existing CPU clock by 16.
> > An additional hint was also given by Neil's clock measurer patch [1]
> > as the GX SoCs explicitly define a "sys_cpu_div16" clock with ID 18,
> > however old u-boot seems to call that CTS_LED_PLL_CLK. The rate of
> > this clock also matches CPU clock divided by 16 on my boards.
> >
> > It's not clear if there is an additional gate for this clock. If there
> > is then it's not documented anywhere.
> >
> >
> > [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/391928.html
> > [1] https://patchwork.kernel.org/patch/10504083/
> >
> > Martin Blumenstingl (2):
> > dt-bindings: clock: meson8b: export the CPU_DIV16 clock
> > clk: meson: meson8b: add the CPU_DIV16 clock
> >
> > drivers/clk/meson/meson8b.c | 12 ++++++++++++
> > drivers/clk/meson/meson8b.h | 2 +-
> > include/dt-bindings/clock/meson8b-clkc.h | 1 +
> > 3 files changed, 14 insertions(+), 1 deletion(-)
> >
>
> Queued for 4.20
sorry, but I found out that this doesn't work.
I'm not sure why I assumed that this has to be a CPU_DIV16 clock but
it's most likely a "divide by 4" (more details below).
so please feel free to revert this / drop the patches until I have
more information
my test-case is:
- CPU frequency scaling is disabled
- TWD timer node is added *without* clock in .dts (it will auto-detect
the clock rate)
- modify the CPU clock in u-boot
- boot Linux
case #1: EC-100 with it's default boot settings:
[ 0.000252] smp_twd: clock not found -2
[ 0.000736] Calibrating local timer... 197.86MHz.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect
duty
clock count count count rate
accuracy phase cycle
---------------------------------------------------------------------------------------------
...
sys_pll_dco 1 1 0 1584000000
0 0 50000
sys_pll 1 1 0 792000000
0 0 50000
cpu_in_sel 1 1 0 792000000
0 0 50000
cpu_scale_out_sel 1 1 0 792000000
0 0 50000
cpu_clk 1 1 0 792000000
0 0 50000
cpu_clk_div4 0 0 0 198000000
0 0 50000
...
case #2: switch the parent of the cpu_in_sel clock to xtal:
m8b_m201_1G#md.l 0xC110419C 1
c110419c: 000000b1 ....
m8b_m201_1G#mw.l 0xC110419C 0xb0 1
m8b_m201_1G#md.l 0xC110419C
c110419c: 000000b0 ....
[ 0.007005] smp_twd: clock not found -2
[ 0.022680] Calibrating local timer... 5.98MHz.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect
duty
clock count count count rate
accuracy phase cycle
---------------------------------------------------------------------------------------------
xtal 4 4 0 24000000
0 0 50000
...
cpu_in_sel 1 1 0 24000000
0 0 50000
cpu_scale_out_sel 1 1 0 24000000
0 0 50000
cpu_clk 1 1 0 24000000
0 0 50000
cpu_clk_div4 0 0 0 6000000
0 0 50000
...
case #3: set cpu_scale_div to cpu_in_sel/4 and use cpu_scale_div as
parent of cpu_scale_out_sel
m8b_m201_1G#mw.l 0xC110419C 0x30 1
m8b_m201_1G#md.l 0xC110415C 1
c110415c: 800016a2 ....
m8b_m201_1G#mw.l 0xC110415C 0x802016A2 1
odroidc#md.l 0xC110415C 1
c110415c: 802016a2 .. .
m8b_m201_1G#mw.l 0xC110419C 0xbd 1
[ 0.001317] smp_twd: clock not found -2
[ 0.003975] Calibrating local timer... 32.93MHz.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect
duty
clock count count count rate
accuracy phase cycle
---------------------------------------------------------------------------------------------
...
sys_pll_dco 1 1 0 1584000000
0 0 50000
sys_pll 1 1 0 792000000
0 0 50000
cpu_in_sel 1 1 0 792000000
0 0 50000
cpu_scale_div 1 1 0 198000000
0 0 50000
cpu_scale_out_sel 1 1 0
198000000 0 0 50000
cpu_clk 1 1 0 198000000
0 0 50000
cpu_clk_div4 0 0 0
49500000 0 0 50000
...
as you can see case dividing "cpu_clk" by 4 works fine in case #1 and #2
however, as soon as cpu_scale_div is involved this doesn't work
anymore: in my test-case the clock is off by 16.5MHz (which is way too
much for a timer)
I am not yet sure *why* this is though
I'll come back with a fixed patchset once I know how it works correctly
Regards
Martin
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD
2018-09-26 9:56 ` Martin Blumenstingl
@ 2018-09-26 9:59 ` Jerome Brunet
0 siblings, 0 replies; 6+ messages in thread
From: Jerome Brunet @ 2018-09-26 9:59 UTC (permalink / raw)
To: linus-amlogic
On Wed, 2018-09-26 at 11:56 +0200, Martin Blumenstingl wrote:
> > Queued for 4.20
>
> sorry, but I found out that this doesn't work.
> I'm not sure why I assumed that this has to be a CPU_DIV16 clock but
> it's most likely a "divide by 4" (more details below).
> so please feel free to revert this / drop the patches until I have
> more information
Dropped for now, feel free to send it again when things get more clear ;)
^ permalink raw reply [flat|nested] 6+ messages in thread
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2018-07-21 17:25 [PATCH 0/2] meson8b: add the CPU_DIV16 clock for the ARM TWD Martin Blumenstingl
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2018-07-21 17:25 ` [PATCH 2/2] clk: meson: meson8b: add " Martin Blumenstingl
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