From: Jerome Brunet <jbrunet@baylibre.com>
To: Chuan Liu <chuan.liu@amlogic.com>
Cc: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 5/8] clk: amlogic: Add A5 clock peripherals controller driver
Date: Mon, 05 Jan 2026 10:14:31 +0100 [thread overview]
Message-ID: <1jldice808.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <425ebeb4-8001-4493-882b-dfee87ed82c8@amlogic.com> (Chuan Liu's message of "Tue, 23 Dec 2025 20:27:39 +0800")
On mar. 23 déc. 2025 at 20:27, Chuan Liu <chuan.liu@amlogic.com> wrote:
>>> +
>>> +#define A5_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \
>> No, adjust your main macro.
>>
>
> Do you mean to unify this into a single macro here? Like this:
>
> #define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \
> MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0)
>
Yes, possibly
--
Jerome
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next prev parent reply other threads:[~2026-01-05 9:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 9:52 [PATCH v4 0/8] clk: amlogic: Add A5 SoC PLLs and Peripheral clock Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 1/8] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2025-12-23 8:59 ` Jerome Brunet
2025-12-23 11:56 ` Chuan Liu
2025-10-28 9:52 ` [PATCH v4 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 3/8] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 4/8] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 5/8] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-12-23 9:16 ` Jerome Brunet
2025-12-23 12:27 ` Chuan Liu
2026-01-05 9:14 ` Jerome Brunet [this message]
2025-10-28 9:52 ` [PATCH v4 6/8] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 7/8] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 8/8] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
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