[PATCH v4 0/4] fix the clock setting for SAR ADC

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Yixun Lan]

patch [1/4]:
  Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
the published datasheets[4] also has wrong description about this.
  This patch should be explicitly merged *before* other patches.

patch [2-4/4]:
  Drop the "sana" clock from SAR ADC module,

  From the hardware perspective, the SAR ADC module doesn't
require "sana" clock to wrok. This should apply to all SoC,
including meson6,8, GXBB, GXL..

Note: the whole patchset series has been tested at GXL-P212 board,
we haven't got any meson6,8 board to test, so I would appreciate
if someone (Martin?) could help to confirm it works there.

Changes since v3 at [3] :
  - fix the missing iio maintainers for patch[2/4]
  - add warning about the dependency, the patch[1/4] should go first
  - update comments

Changes since v2 at [2] :
  - explicitly point out 'sana' clock is not required for saradc, and drop them
  - update comments, as the published datasheet is wrong
 
Changes since v1 at [1] :
  - correct SAR ADC/SANA clock gate bit

[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005221.html

[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005242.html

[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005252.html
    http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005257.html
    http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005253.html
    http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005254.html
    http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005255.html


[4] GXBB v1.1.4, page 57
      http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
    GXL v0.3_20170314
      http://www.mediafire.com/file/5bpt054va5ut7v9/S905X_Datasheet_V0.3_20170314publicversion-Wesion.pdf


Xingyu Chen (3):
  iio: adc: meson-saradc: remove irrelevant clock "sana"
  dt-bindings: iio: adc: update the doc for SAR ADC
  ARM64: dts: meson: drop "sana" clock from SAR ADC

Yixun Lan (1):
  clk: meson: gxbb: fix wrong clock for SARADC/SANA

 .../bindings/iio/adc/amlogic,meson-saradc.txt        |  1 -
 arch/arm/boot/dts/meson8.dtsi                        |  5 ++---
 arch/arm/boot/dts/meson8b.dtsi                       |  5 ++---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          |  3 +--
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi           |  3 +--
 drivers/clk/meson/gxbb.c                             |  4 ++--
 drivers/iio/adc/meson_saradc.c                       | 20 --------------------
 7 files changed, 8 insertions(+), 33 deletions(-)

-- 
2.14.1

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Martin Blumenstingl]

Hi Yixun,

On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> patch [1/4]:
>   Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
> the published datasheets[4] also has wrong description about this.
>   This patch should be explicitly merged *before* other patches.
>
> patch [2-4/4]:
>   Drop the "sana" clock from SAR ADC module,
I agree with Jerome that patch 2/4 should be applied last.
when I wrote the driver I couldn't get it to work on my GXBB board
(which unfortunately has died since then) because the clocks were
disabled (they weren't enabled by the bootloader). people who are
using an old .dtb would get the same problem again until the clock
driver is merged

>   From the hardware perspective, the SAR ADC module doesn't
> require "sana" clock to wrok. This should apply to all SoC,
> including meson6,8, GXBB, GXL..
thank you for clarifying this!

> Note: the whole patchset series has been tested at GXL-P212 board,
> we haven't got any meson6,8 board to test, so I would appreciate
> if someone (Martin?) could help to confirm it works there.
I can test this on a Meson8b and a Meson8m2 board on the weekend -
I'll let you know about the results


Regards
Martin

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Jonathan Cameron]

On Tue, 7 Nov 2017 22:36:00 +0100
Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> Hi Yixun,
> 
> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> > patch [1/4]:
> >   Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
> > the published datasheets[4] also has wrong description about this.
> >   This patch should be explicitly merged *before* other patches.
> >
> > patch [2-4/4]:
> >   Drop the "sana" clock from SAR ADC module,  
> I agree with Jerome that patch 2/4 should be applied last.

Let me know when I should take this.

Thanks,

Jonathan

> when I wrote the driver I couldn't get it to work on my GXBB board
> (which unfortunately has died since then) because the clocks were
> disabled (they weren't enabled by the bootloader). people who are
> using an old .dtb would get the same problem again until the clock
> driver is merged
> 
> >   From the hardware perspective, the SAR ADC module doesn't
> > require "sana" clock to wrok. This should apply to all SoC,
> > including meson6,8, GXBB, GXL..  
> thank you for clarifying this!
> 
> > Note: the whole patchset series has been tested at GXL-P212 board,
> > we haven't got any meson6,8 board to test, so I would appreciate
> > if someone (Martin?) could help to confirm it works there.  
> I can test this on a Meson8b and a Meson8m2 board on the weekend -
> I'll let you know about the results
> 
> 
> Regards
> Martin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Martin Blumenstingl]

Hi Yixun,

On Tue, Nov 7, 2017 at 10:36 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Hi Yixun,
>
> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
>> patch [1/4]:
>>   Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
>> the published datasheets[4] also has wrong description about this.
>>   This patch should be explicitly merged *before* other patches.
>>
>> patch [2-4/4]:
>>   Drop the "sana" clock from SAR ADC module,
> I agree with Jerome that patch 2/4 should be applied last.
> when I wrote the driver I couldn't get it to work on my GXBB board
> (which unfortunately has died since then) because the clocks were
> disabled (they weren't enabled by the bootloader). people who are
> using an old .dtb would get the same problem again until the clock
> driver is merged
>
>>   From the hardware perspective, the SAR ADC module doesn't
>> require "sana" clock to wrok. This should apply to all SoC,
>> including meson6,8, GXBB, GXL..
> thank you for clarifying this!
>
>> Note: the whole patchset series has been tested at GXL-P212 board,
>> we haven't got any meson6,8 board to test, so I would appreciate
>> if someone (Martin?) could help to confirm it works there.
> I can test this on a Meson8b and a Meson8m2 board on the weekend -
> I'll let you know about the results
the ADC still works fine with this series applied on my Meson8m2 board
as well as my Meson8b EC-100
I added my "Reviewed-by" and "Acked-by" to the corresponding patches
(with a change request on the .dts patch)

Thank you for fixing this!


Regards
Martin

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Yixun Lan]

On 11/11/17 08:37, Jonathan Cameron wrote:
> On Tue, 7 Nov 2017 22:36:00 +0100
> Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> 
>> Hi Yixun,
>>
>> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
>>> patch [1/4]:
>>>   Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
>>> the published datasheets[4] also has wrong description about this.
>>>   This patch should be explicitly merged *before* other patches.
>>>
>>> patch [2-4/4]:
>>>   Drop the "sana" clock from SAR ADC module,  
>> I agree with Jerome that patch 2/4 should be applied last.
> 
> Let me know when I should take this.
> 
> Thanks,
> 
> Jonathan
> 
>> when I wrote the driver I couldn't get it to work on my GXBB board
>> (which unfortunately has died since then) because the clocks were
>> disabled (they weren't enabled by the bootloader). people who are
>> using an old .dtb would get the same problem again until the clock
>> driver is merged
>>
>>>   From the hardware perspective, the SAR ADC module doesn't
>>> require "sana" clock to wrok. This should apply to all SoC,
>>> including meson6,8, GXBB, GXL..  
>> thank you for clarifying this!
>>
>>> Note: the whole patchset series has been tested at GXL-P212 board,
>>> we haven't got any meson6,8 board to test, so I would appreciate
>>> if someone (Martin?) could help to confirm it works there.  
>> I can test this on a Meson8b and a Meson8m2 board on the weekend -
>> I'll let you know about the results
>>
>>
>> Regards
>> Martin
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

Hi Jonathan Cameron & Kevin Hilman:

 since the clk part patch has been applied[1], can we proceed with others?

to Jonathan:
I think the iio part(patch [2/4]) should be merged via your iio tree?
see [2]

to Kevin:
could you take the DTS part? see [3], and the patch [4/4] has a rework
version, see [4], to separate dt64 vs dt32 device tree.


[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005472.html

[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005264.html

[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005265.html

[4]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005304.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005305.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005306.html

Yixun

[PATCH v4 0/4] fix the clock setting for SAR ADC

[Jonathan Cameron]

On Tue, 28 Nov 2017 21:11:29 +0800
Yixun Lan <yixun.lan@amlogic.com> wrote:

> On 11/11/17 08:37, Jonathan Cameron wrote:
> > On Tue, 7 Nov 2017 22:36:00 +0100
> > Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> >   
> >> Hi Yixun,
> >>
> >> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:  
> >>> patch [1/4]:
> >>>   Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
> >>> the published datasheets[4] also has wrong description about this.
> >>>   This patch should be explicitly merged *before* other patches.
> >>>
> >>> patch [2-4/4]:
> >>>   Drop the "sana" clock from SAR ADC module,    
> >> I agree with Jerome that patch 2/4 should be applied last.  
> > 
> > Let me know when I should take this.
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> >> when I wrote the driver I couldn't get it to work on my GXBB board
> >> (which unfortunately has died since then) because the clocks were
> >> disabled (they weren't enabled by the bootloader). people who are
> >> using an old .dtb would get the same problem again until the clock
> >> driver is merged
> >>  
> >>>   From the hardware perspective, the SAR ADC module doesn't
> >>> require "sana" clock to wrok. This should apply to all SoC,
> >>> including meson6,8, GXBB, GXL..    
> >> thank you for clarifying this!
> >>  
> >>> Note: the whole patchset series has been tested at GXL-P212 board,
> >>> we haven't got any meson6,8 board to test, so I would appreciate
> >>> if someone (Martin?) could help to confirm it works there.    
> >> I can test this on a Meson8b and a Meson8m2 board on the weekend -
> >> I'll let you know about the results
> >>
> >>
> >> Regards
> >> Martin
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> >> the body of a message to majordomo at vger.kernel.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html  
> > 
> > 
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic
> > 
> > .
> >   
> 
> Hi Jonathan Cameron & Kevin Hilman:
> 
>  since the clk part patch has been applied[1], can we proceed with others?
> 
> to Jonathan:
> I think the iio part(patch [2/4]) should be merged via your iio tree?
> see [2]
I've applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to play with it.  It also makes sense for me to
take the dts binding update as it goes with the driver change. 

Hence I've just left patch 4 for Kevin.  Doesn't matter if this crosses
with Kevin also taking patch 3 though as it'll get sorted out automatically
by git later anyway.

Thanks

Jonathan
> 
> to Kevin:
> could you take the DTS part? see [3], and the patch [4/4] has a rework
> version, see [4], to separate dt64 vs dt32 device tree.
> 
> 
> [1]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005472.html
> 
> [2]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005264.html
> 
> [3]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005265.html
> 
> [4]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005304.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005305.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005306.html
> 
> Yixun
>