From: Jonathan Cameron <jic23@kernel.org>
To: andy.shevchenko@gmail.com
Cc: George Stark <gnstark@sberdevices.ru>,
lars@metafoo.de, neil.armstrong@linaro.org, khilman@baylibre.com,
jbrunet@baylibre.com, martin.blumenstingl@googlemail.com,
andriy.shevchenko@linux.intel.com, nuno.sa@analog.com,
linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
kernel@sberdevices.ru
Subject: Re: [PATCH v3] meson saradc: fix clock divider mask length
Date: Sat, 10 Jun 2023 18:59:18 +0100 [thread overview]
Message-ID: <20230610185918.7c85b66e@jic23-huawei> (raw)
In-Reply-To: <ZH-4qsNcLGiQFiSE@surfacebook>
On Wed, 7 Jun 2023 01:52:26 +0300
andy.shevchenko@gmail.com wrote:
> Tue, Jun 06, 2023 at 07:53:57PM +0300, George Stark kirjoitti:
> > According to datasheets of supported meson SOCs length of ADC_CLK_DIV
>
> the datasheets
>
> > field is 6 bits long. Although all supported SOCs have the register
>
> 6-bit
>
> > with that field documented later SOCs use external clock rather than
> > ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> s/SOC/SoC/g, and mind the grammar period at the end.
>
> I believe Jonathan can fix when applying this, no need to resend unless
> he asks for it.
>
Indeed - done and applied to the fixes-togreg branch of iio.git + marked it
for stable inclusion.
Thanks,
Jonathan
> FWIW,
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>
> > Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> > Signed-off-by: George Stark <GNStark@sberdevices.ru>
> > ---
> > Changelog:
> >
> > v1 -> v2:
> > * Update commit message
> > v2 -> v3:
> > * Update commit message
> > ---
> > drivers/iio/adc/meson_saradc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> > index 85b6826cc10c..b93ff42b8c19 100644
> > --- a/drivers/iio/adc/meson_saradc.c
> > +++ b/drivers/iio/adc/meson_saradc.c
> > @@ -72,7 +72,7 @@
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> > #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> > - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> > + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> >
> > --
> > 2.38.4
> >
>
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prev parent reply other threads:[~2023-06-10 17:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 16:53 [PATCH v3] meson saradc: fix clock divider mask length George Stark
2023-06-06 19:14 ` Martin Blumenstingl
2023-06-06 22:52 ` andy.shevchenko
2023-06-10 17:59 ` Jonathan Cameron [this message]
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