From: Conor Dooley <conor@kernel.org>
To: Jian Hu <jian.hu@amlogic.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Chuan Liu <chuan.liu@amlogic.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Dmitry Rokosov <ddrokosov@sberdevices.ru>,
robh+dt <robh+dt@kernel.org>, Rob Herring <robh@kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
linux-amlogic <linux-amlogic@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL clock controller
Date: Fri, 9 May 2025 17:09:35 +0100 [thread overview]
Message-ID: <20250509-straddle-parish-92306b78486b@spud> (raw)
In-Reply-To: <20250509074825.1933254-2-jian.hu@amlogic.com>
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On Fri, May 09, 2025 at 07:48:19AM +0000, Jian Hu wrote:
> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Looks like Rob's comments got resolved,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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next prev parent reply other threads:[~2025-05-09 18:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu
2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-05-09 16:09 ` Conor Dooley [this message]
2025-05-09 7:48 ` [PATCH v3 2/6] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
2025-05-09 7:48 ` [PATCH v3 3/6] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
2025-05-09 7:48 ` [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-05-14 7:52 ` Jerome Brunet
2025-06-12 13:02 ` Jian Hu
2025-06-16 16:27 ` Jerome Brunet
2025-06-25 2:52 ` Jian Hu
2025-06-25 7:46 ` Jerome Brunet
2025-07-03 3:42 ` Jian Hu
2025-05-09 7:48 ` [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock Jian Hu
2025-05-14 7:39 ` Jerome Brunet
[not found] ` <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com>
2025-06-16 16:28 ` Jerome Brunet
2025-06-20 9:21 ` Jian Hu
2025-05-09 7:48 ` [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
2025-05-14 8:00 ` Jerome Brunet
2025-06-13 9:39 ` Jian Hu
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