From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D606CD11DD for ; Fri, 29 Mar 2024 16:07:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:Reply-To:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:Subject: From:MIME-Version:Date:Message-ID:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=O+JBwAlNJRg26j5tJmxB2IGiGoMZUFY3bDBJl7/y7Xo=; b=pSSF1AyeosPfnUFxesRGpgtaI3 /JoOroo6Ovet+NH+Z0Cj2gSkMSEpdXAcJTECDHkWQiaeVeatKaZ3suCbTXVB06vW0mYXSBZLh4zXA IrBC1WDzdnANLaTRTbhxXLytBzpQxptw0EcIfQYLOqtZlkmGswxDOrKWtjUzmOmu6REi5xv/W0RBh 8B0eQEitgIC0gGZl6HcsLl1PNt3U0cF10GSiC98KCFkGOqOe5RhKgkUR9d5wmlon34xmMB8MW+FLy +CxqcwK9nLGm0JxUcPP6B1oM9n+DoUc5jsnDQcWJS0qZJbpQ5IKZ2xnSGGDayLoPE6tSUmgpA7he9 fqP48Awg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqElG-00000001FYu-0hzo; Fri, 29 Mar 2024 16:07:22 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqElC-00000001FWP-1BXw for linux-amlogic@lists.infradead.org; Fri, 29 Mar 2024 16:07:20 +0000 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-33ececeb19eso1201403f8f.3 for ; Fri, 29 Mar 2024 09:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711728435; x=1712333235; darn=lists.infradead.org; h=content-transfer-encoding:in-reply-to:organization:autocrypt :content-language:references:cc:to:subject:reply-to:from:user-agent :mime-version:date:message-id:from:to:cc:subject:date:message-id :reply-to; bh=NkjrKE6IuMRJrcH8UKGD1gXPrQ5QNm+lu1/8bGgH4ic=; b=B0jUj+RJkRIS1GjbqNCwanhGYJ4CciLpGfQfDXvHFju/ZFliMmlibyb5DY2EW9yYts a1rDK7/GOoaCF4S38FiTjdsBDdt+bETn6O9kuxpkd9tbceK5QkLQVAH4jj72vn4wT7kp vkSXEnnhybtLqVdyZEOT6pQRokB70k3s1y89FQXtkKJbUZx5LRmz8c4V0Q/PwiGXgZmd s1uG1PZFzW5pjd8BYp/bWtnyakpji1jiUj/QLISxia/0CODXSFyBs9tGYChbNWUeSkMZ ASfU8diCkOm1rR6GWKd2z/hLqfqM0h45wyb+DudsUTPGRYPhdYaCAmieurwc4zNW/4nA Anxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711728435; x=1712333235; h=content-transfer-encoding:in-reply-to:organization:autocrypt :content-language:references:cc:to:subject:reply-to:from:user-agent :mime-version:date:message-id:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=NkjrKE6IuMRJrcH8UKGD1gXPrQ5QNm+lu1/8bGgH4ic=; b=iI3AxLIsQIX/CZDb/IrrD27kd5yvpUgE2AU4Ezo0xNtJjnK1x+R2evyW1Sap4Q91Ee 35O8OUG13udw+qar5LDHVnvcvofxlTOZic/zYc9FKodf6KhlkPsrKxl02Qz35NJtWF69 XfGHJ/maQDmEcK1TwJaqbgEcHbn0ai6vGutrMGcjD/i0ffYJAr5USzis9WGJYDvb+44D ZtQsMLYKJ/JOQWBL6CgU/BKA/QCCFSfSvGGvfH8yyJhNNrkl6Uvm4znr3V8s3jure3aE RepjQNeeDm2hKQHQcXA+kuXsGsR4NWgelvskWx+78nKB7ABtxNzEu0TI5QeNJ+k5NsdG ecmw== X-Forwarded-Encrypted: i=1; AJvYcCUfsZHmoE4YjD4Ds4rgmE/5/3dDqmAwEXkS+MUpjSlnxgLC9Y2xCYaJtQPFYKt9WWEbERE/3XVcPX+vA91h2ZylYEE8hPOgb2HAFCj5BwS1N38= X-Gm-Message-State: AOJu0YxsRJBN+P7DRS1/u75/ylMKtbaUUCAL+H3aybEOZhJWU7LsGEAg CJMFZ6esXSineoIo031HIoPt6w7unuDaxIbLpLBOQqcd4b9hgQxGu19CrLDewjc= X-Google-Smtp-Source: AGHT+IFuCPG+afiseNRtV6C8sMI1cvLkX2q2Mn+253xYnh8lGDw5llJy33URLv+YoNPPIFIxTDY2Ag== X-Received: by 2002:a5d:4b08:0:b0:341:8c2e:5001 with SMTP id v8-20020a5d4b08000000b003418c2e5001mr1696413wrq.64.1711728435308; Fri, 29 Mar 2024 09:07:15 -0700 (PDT) Received: from ?IPV6:2a01:e0a:982:cbb0:3cd8:c97b:1468:c232? ([2a01:e0a:982:cbb0:3cd8:c97b:1468:c232]) by smtp.gmail.com with ESMTPSA id k17-20020adff5d1000000b00341b7388dafsm4478433wrp.77.2024.03.29.09.07.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Mar 2024 09:07:14 -0700 (PDT) Message-ID: <7424b114-05df-4603-88ac-ba59aec45c9e@linaro.org> Date: Fri, 29 Mar 2024 17:07:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Subject: Re: [PATCH v11 2/7] clk: meson: add vclk driver To: Jerome Brunet Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Nicolas Belin , Jagan Teki , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org References: <20240325-amlogic-v6-4-upstream-dsi-ccf-vim3-v11-0-04f55de44604@linaro.org> <20240325-amlogic-v6-4-upstream-dsi-ccf-vim3-v11-2-04f55de44604@linaro.org> <1jzfuh8bd7.fsf@starbuckisacylon.baylibre.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <1jzfuh8bd7.fsf@starbuckisacylon.baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_090718_434771_91EF1FEE X-CRM114-Status: GOOD ( 22.22 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: neil.armstrong@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On 29/03/2024 13:33, Jerome Brunet wrote: > > On Mon 25 Mar 2024 at 12:09, Neil Armstrong wrote: > >> The VCLK and VCLK_DIV clocks have supplementary bits. >> >> The VCLK gate has a "SOFT RESET" bit to toggle after the whole >> VCLK sub-tree rate has been set, this is implemented in >> the gate enable callback. >> >> The VCLK_DIV clocks as enable and reset bits used to disable >> and reset the divider, associated with CLK_SET_RATE_GATE it ensures >> the rate is set while the divider is disabled and in reset mode. >> >> The VCLK_DIV enable bit isn't implemented as a gate since it's part >> of the divider logic and vendor does this exact sequence to ensure >> the divider is correctly set. > > checkpatch reports a few easy CHECKs and one WARNING. > Could you please fix these ? > > Other than that, It looks OK. Ack thx Neil > >> >> Signed-off-by: Neil Armstrong >> --- >> drivers/clk/meson/Kconfig | 4 ++ >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/vclk.c | 141 +++++++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/meson/vclk.h | 51 ++++++++++++++++ >> 4 files changed, 197 insertions(+) >> >> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig >> index 29ffd14d267b..8a9823789fa3 100644 >> --- a/drivers/clk/meson/Kconfig >> +++ b/drivers/clk/meson/Kconfig >> @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV >> tristate >> select COMMON_CLK_MESON_REGMAP >> >> +config COMMON_CLK_MESON_VCLK >> + tristate >> + select COMMON_CLK_MESON_REGMAP >> + >> config COMMON_CLK_MESON_CLKC_UTILS >> tristate >> >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index 9ee4b954c896..9ba43fe7a07a 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o >> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o >> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o >> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o >> +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o >> >> # Amlogic Clock controllers >> >> diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c >> new file mode 100644 >> index 000000000000..3ea813a0a995 >> --- /dev/null >> +++ b/drivers/clk/meson/vclk.c >> @@ -0,0 +1,141 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2024 Neil Armstrong >> + */ >> + >> +#include >> +#include "vclk.h" >> + >> +/* The VCLK gate has a supplementary reset bit to pulse after ungating */ >> + >> +static inline struct meson_vclk_gate_data * >> +clk_get_meson_vclk_gate_data(struct clk_regmap *clk) >> +{ >> + return (struct meson_vclk_gate_data *)clk->data; >> +} >> + >> +static int meson_vclk_gate_enable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); >> + >> + meson_parm_write(clk->map, &vclk->enable, 1); >> + >> + /* Do a reset pulse */ >> + meson_parm_write(clk->map, &vclk->reset, 1); >> + meson_parm_write(clk->map, &vclk->reset, 0); >> + >> + return 0; >> +} >> + >> +static void meson_vclk_gate_disable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); >> + >> + meson_parm_write(clk->map, &vclk->enable, 0); >> +} >> + >> +static int meson_vclk_gate_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); >> + >> + return meson_parm_read(clk->map, &vclk->enable); >> +} >> + >> +const struct clk_ops meson_vclk_gate_ops = { >> + .enable = meson_vclk_gate_enable, >> + .disable = meson_vclk_gate_disable, >> + .is_enabled = meson_vclk_gate_is_enabled, >> +}; >> +EXPORT_SYMBOL_GPL(meson_vclk_gate_ops); >> + >> +/* The VCLK Divider has supplementary reset & enable bits */ >> + >> +static inline struct meson_vclk_div_data * >> +clk_get_meson_vclk_div_data(struct clk_regmap *clk) >> +{ >> + return (struct meson_vclk_div_data *)clk->data; >> +} >> + >> +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw, >> + unsigned long prate) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + >> + return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div), >> + vclk->table, vclk->flags, vclk->div.width); >> +} >> + >> +static int meson_vclk_div_determine_rate(struct clk_hw *hw, >> + struct clk_rate_request *req) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + >> + return divider_determine_rate(hw, req, vclk->table, vclk->div.width, >> + vclk->flags); >> +} >> + >> +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate, >> + unsigned long parent_rate) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + int ret; >> + >> + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width, >> + vclk->flags); >> + if (ret < 0) >> + return ret; >> + >> + meson_parm_write(clk->map, &vclk->div, ret); >> + >> + return 0; >> +}; >> + >> +static int meson_vclk_div_enable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + >> + /* Unreset the divider when ungating */ >> + meson_parm_write(clk->map, &vclk->reset, 0); >> + meson_parm_write(clk->map, &vclk->enable, 1); >> + >> + return 0; >> +} >> + >> +static void meson_vclk_div_disable(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + >> + /* Reset the divider when gating */ >> + meson_parm_write(clk->map, &vclk->enable, 0); >> + meson_parm_write(clk->map, &vclk->reset, 1); >> +} >> + >> +static int meson_vclk_div_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_regmap *clk = to_clk_regmap(hw); >> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); >> + >> + return meson_parm_read(clk->map, &vclk->enable); >> +} >> + >> +const struct clk_ops meson_vclk_div_ops = { >> + .recalc_rate = meson_vclk_div_recalc_rate, >> + .determine_rate = meson_vclk_div_determine_rate, >> + .set_rate = meson_vclk_div_set_rate, >> + .enable = meson_vclk_div_enable, >> + .disable = meson_vclk_div_disable, >> + .is_enabled = meson_vclk_div_is_enabled, >> +}; >> +EXPORT_SYMBOL_GPL(meson_vclk_div_ops); >> + >> +MODULE_DESCRIPTION("Amlogic vclk clock driver"); >> +MODULE_AUTHOR("Neil Armstrong "); >> +MODULE_LICENSE("GPL v2"); >> diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h >> new file mode 100644 >> index 000000000000..20b0b181db09 >> --- /dev/null >> +++ b/drivers/clk/meson/vclk.h >> @@ -0,0 +1,51 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (c) 2024 Neil Armstrong >> + */ >> + >> +#ifndef __VCLK_H >> +#define __VCLK_H >> + >> +#include "clk-regmap.h" >> +#include "parm.h" >> + >> +/** >> + * struct meson_vclk_gate_data - vclk_gate regmap backed specific data >> + * >> + * @enable: vclk enable field >> + * @reset: vclk reset field >> + * @flags: hardware-specific flags >> + * >> + * Flags: >> + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored >> + */ >> +struct meson_vclk_gate_data { >> + struct parm enable; >> + struct parm reset; >> + u8 flags; >> +}; >> + >> +extern const struct clk_ops meson_vclk_gate_ops; >> + >> +/** >> + * struct meson_vclk_div_data - vclk_div regmap back specific data >> + * >> + * @div: divider field >> + * @enable: vclk divider enable field >> + * @reset: vclk divider reset field >> + * @table: array of value/divider pairs, last entry should have div = 0 >> + * >> + * Flags: >> + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored >> + */ >> +struct meson_vclk_div_data { >> + struct parm div; >> + struct parm enable; >> + struct parm reset; >> + const struct clk_div_table *table; >> + u8 flags; >> +}; >> + >> +extern const struct clk_ops meson_vclk_div_ops; >> + >> +#endif /* __VCLK_H */ > > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic