[PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase

Vyacheslav Bocharov
2022-11-10T15:01:50Z

- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
clock with values:
0: CLK_PHASE_0 - 0 phase
1: CLK_PHASE_90 - 90 phase
2: CLK_PHASE_180 - 180 phase
3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index ccc5358db131..98c89c5b3455 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -25,6 +25,12 @@ Required properties:
Optional properties:
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
DRAM memory, like on the G12A dedicated SDIO controller.
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
+ 0: CLK_PHASE_0 - 0 phase
+ 1: CLK_PHASE_90 - 90 phase
+ 2: CLK_PHASE_180 - 180 phase
+ 3: CLK_PHASE_270 - 270 phase
+ By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.

Example:

@@ -36,4 +42,5 @@ Example:
clock-names = "core", "clkin0", "clkin1";
pinctrl-0 = <&emmc_pins>;
resets = <&reset RESET_SD_EMMC_A>;
+ amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
};
--
2.30.2