From: Xianwei Zhao <xianwei.zhao@amlogic.com>
To: Rob Herring <robh@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node
Date: Thu, 15 May 2025 11:04:42 +0800 [thread overview]
Message-ID: <b58ce27b-6e32-4fa6-ba31-7e1b25e1bdd6@amlogic.com> (raw)
In-Reply-To: <20250514131022.GA1833633-robh@kernel.org>
Hi Rob,
Thanks for your reply.
On 2025/5/14 21:10, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, May 14, 2025 at 03:01:33PM +0800, Xianwei Zhao wrote:
>> Add pinctrl device to support Amlogic S7.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++
>> 1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> index f0c172681bd1..924f10aff269 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
>> @@ -6,6 +6,7 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>>
>> / {
>> cpus {
>> @@ -94,6 +95,86 @@ uart_b: serial@7a000 {
>> clock-names = "xtal", "pclk", "baud";
>> status = "disabled";
>> };
>> +
>> + periphs_pinctrl: pinctrl {
>
> If you have non-boolean ranges, then this should have a unit address
> (@4000).
>
Will add a unit address for node.
>> + compatible = "amlogic,pinctrl-s7";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
> Doesn't look like you need 64-bits of address and size. 1 cell is
> enough.
>
Krzysztof raised this question in the definition of binding stage.
https://lore.kernel.org/all/012cfaca-e8f5-4614-9393-a4a46a797adb@amlogic.com/
>> + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
>
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next prev parent reply other threads:[~2025-05-15 3:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 7:01 [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 1/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7 Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 2/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 3/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 4/8] pinctrl: meson: a4: remove special data processing Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 5/8] pinctrl: meson: support amlogic S6/S7/S7D SoC Xianwei Zhao via B4 Relay
2025-05-14 20:18 ` kernel test robot
2025-05-14 7:01 ` [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node Xianwei Zhao via B4 Relay
2025-05-14 13:10 ` Rob Herring
2025-05-15 3:04 ` Xianwei Zhao [this message]
2025-05-14 7:01 ` [PATCH 7/8] dts: arm64: amlogic: add S7D " Xianwei Zhao via B4 Relay
2025-05-14 7:01 ` [PATCH 8/8] dts: arm64: amlogic: add S6 " Xianwei Zhao via B4 Relay
2025-05-14 13:11 ` [PATCH 0/8] Add support for Amlogic S7/S7D/S6 pinctrl Rob Herring (Arm)
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