Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

From: Zhentao Guo <zhentao.guo@amlogic.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org
Subject: Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder
Date: Fri, 13 Feb 2026 17:14:12 +0800	[thread overview]
Message-ID: <df5ec40a-8674-4983-a912-8aa2bbfd2da7@amlogic.com> (raw)
In-Reply-To: <58d57a6c-7c69-4f5b-a4c2-f34ef0238511@kernel.org>

Hi

在 2026/2/13 16:55, Krzysztof Kozlowski 写道:
> On 13/02/2026 09:31, Zhentao Guo wrote:
>>>>>> +  power-domains:
>>>>>> +    maxItems: 2
>>>>>> +
>>>>>> +  power-domain-names:
>>>>>> +    items:
>>>>>> +      - const: vdec
>>>>>> +      - const: hevc
>>>>>> +
>>>>>> +  resets:
>>>>>> +    maxItems: 1
>>>>>> +
>>>>>> +  amlogic,canvas:
>>>>>> +    description: should point to a canvas provider node
>>>>> Why? What for?
>>>>>
>>>>> What is canvas provider?
>>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
>>> What is this "canvas" device.
>> You can think of canvas as the agent through which the decoder hardware
>> accesses DDR.
> AGAIN:
>
> What is the canvas device. Describe or point me to bindings describing
> it. Your current bindings say that canvas is "a collection of metadata
> that describes a pixel buffer" so there is no way it handles DDR access.
>
> NAK
I will rewrite this description based on your feedback after I 
thoroughly understand the role of the canvas device.
>>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>>> needs to access DDR through canvas IP, so we need to reference the
>>> Why decoder cannot access DDR directly?
>> The internal topology of the S4 chip is designed this way, we don't know
>> why our VLSI colleauges designed like this. But similar designs have
>> been removed in subsequent chips, eliminating the need to rely on a
>> common hardware IP.
> Quite poor explanation. Based on this, this as well could be entry in
> device reg lists.
>
> Anyway, I am done guessing, explain properly the hardware instead of
> answering with half-baked responses just so I will go away.
Okay, please give me some time and I'll ask our colleagues about this.  
I you reply you basedon this message then.
> Best regards,
> Krzysztof

BRs

Zhentao


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