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([2001:861:44c0:66c0:ced2:397a:bee8:75f5]) by smtp.gmail.com with ESMTPSA id i8sm4537859wry.45.2022.01.20.05.28.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jan 2022 05:28:12 -0800 (PST) Subject: Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver To: Jagan Teki Cc: daniel@ffwll.ch, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org References: <20200907081825.1654-1-narmstrong@baylibre.com> <20200907081825.1654-7-narmstrong@baylibre.com> <70d1af3f-bc00-4afd-1157-1cf70d3b2c88@baylibre.com> From: Neil Armstrong Organization: Baylibre Message-ID: Date: Thu, 20 Jan 2022 14:28:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220120_052814_321763_338FC578 X-CRM114-Status: GOOD ( 22.41 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Jagan, On 20/01/2022 12:03, Jagan Teki wrote: > On Wed, Jan 12, 2022 at 1:49 PM Neil Armstrong wrote: >> >> Hi, >> >> On 12/01/2022 08:24, Jagan Teki wrote: >>> Hi Neil, >>> >>> On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong wrote: >>>> >>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom >>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other >>>> Amlogic SoCs. >>>> >>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided >>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the >>>> Analog PHY in the proper way. >>>> >>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock >>>> is derived and feeds the ENCL encoder and the VIU pixel reader. >>>> >>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the >>>> DW-MIPI-DSI transceiver. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >> >> [..] >> >>>> + >>>> +static const struct component_ops meson_dw_mipi_dsi_ops = { >>>> + .bind = meson_dw_mipi_dsi_bind, >>>> + .unbind = meson_dw_mipi_dsi_unbind, >>>> +}; >>> >>> Do you thought of non-component based meson DSI like STM DSI? It >>> require changes from meson drm but just to understand if you have any >>> such plan. >> >> I have no such plans for now, note this serie has been rewritten at [1] but still >> with based with components. >> >> If worth it, the plan is to get it with components and than yes if it's simpler >> drop components completely. > > Dropping components make the pipeline well suited for bridges as we > are moving bridge-driven pipelines in other areas. > >> >> I'll have a look at how ST does > > ST has no components. As I said above, eventually there would be > common bridge driver for dw-mipi-dsi if meson and rockchip moving away > from components. ST driver is much more simpler. And having a common dw-mipi-dsi is unreal since each HW has a different glue HW me must handle. Even if we moved all the glue handling under drm/bridge/synopsys, we would need a different set of callbacks for each HW for each compatible which is basically the actual situation except components. Neil > > Thanks, > Jagan. > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic