From: khilman@baylibre.com (Kevin Hilman)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v2 2/2] pinctrl: meson: meson8b: rename the NAND DQS pin definitions
Date: Mon, 03 Apr 2017 09:08:45 -0700 [thread overview]
Message-ID: <m28tnha2ya.fsf@baylibre.com> (raw)
In-Reply-To: <20170401135922.1288-3-martin.blumenstingl@googlemail.com> (Martin Blumenstingl's message of "Sat, 1 Apr 2017 15:59:22 +0200")
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1.
> However, they both seem to have the same function, just exposed on
> different pins (unlike the ethernet TX pins for example, where there's
> eth_txd0..3 - all of these can be active at the same time as they are
> different data lines).
> Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that
> it's the same functionality just exposed on different pins (BOOT_15 and
> BOOT_18).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Since we don't yet have any users of these pins, LGTM.
Acked-by: Kevin Hilman <khilman@baylibre.com>
next prev parent reply other threads:[~2017-04-03 16:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-25 18:43 [PATCH 0/1] pinctrl-meson8b: fix the NAND DQS pin definitions Martin Blumenstingl
2017-03-25 18:43 ` [PATCH 1/1] pinctrl: meson: meson8b: fix the NAND DQS pins Martin Blumenstingl
2017-03-28 15:09 ` Kevin Hilman
2017-03-28 21:26 ` Martin Blumenstingl
2017-04-01 13:59 ` [PATCH v2 0/2] pinctrl-meson8b: fix the NAND DQS pin definitions Martin Blumenstingl
2017-04-01 13:59 ` [PATCH v2 1/2] pinctrl: meson: meson8b: fix the NAND DQS pins Martin Blumenstingl
2017-04-03 16:07 ` Kevin Hilman
2017-04-07 7:29 ` Linus Walleij
2017-04-01 13:59 ` [PATCH v2 2/2] pinctrl: meson: meson8b: rename the NAND DQS pin definitions Martin Blumenstingl
2017-04-03 16:08 ` Kevin Hilman [this message]
2017-04-07 7:31 ` Linus Walleij
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