* [PATCH v3 00/11] Support for coresight ETMv4 tracer
@ 2015-05-06 15:27 Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 03/11] coresight-etm4x: Controls pertaining to the reset, mode, pe and events Mathieu Poirier
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw)
To: gregkh
Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia,
zhang.chunyan, mathieu.poirier
Please find in this patchset a driver implementation that conforms
to the coresight framework and provide support for the Embedded
Trace Macrocell version 4.
Regards,
Mathieu
---
Changes for v3:
- Fixed cosmetic detail in Kconfig.
- Removed THIS_MODULE from driver declaration.
- Removed MODULE_XYX() declarations at the bottom of the file.
---
Pratik Patel (11):
coresight-etm4x: Adding CoreSight ETM4x driver
coresight-etm4x: Controls pertaining to tracer configuration
coresight-etm4x: Controls pertaining to the reset, mode, pe and events
coresight-etm4x: Controls pertaining to various configuration options
coresight-etm4x: Controls pertaining to the ViewInst register
coresight-etm4x: Controls pertaining to the address comparator
functions
coresight-etm4x: Controls pertaining to the sequencer functions
coresight-etm4x: Controls pertaining to the counter functions
coresight-etm4x: Controls pertaining to the selection of resources
coresight-etm4x: Controls pertaining to the context ID functions
coresight-etm4x: Controls pertaining to the VM ID functions
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 295 +++
drivers/hwtracing/coresight/Kconfig | 11 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-etm4x.c | 2740 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-etm4x.h | 391 +++
5 files changed, 3438 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.h
--
1.9.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 03/11] coresight-etm4x: Controls pertaining to the reset, mode, pe and events 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 04/11] coresight-etm4x: Controls pertaining to various configuration options Mathieu Poirier ` (6 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: mathieu.poirier, linux-api, linux-kernel, zhang.chunyan, linux-arm-kernel, kaixu.xia From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to: . set the tracing entity with default values. . set various mode associated to the tracing entity. . select the processing entity the tracing entity relates to. . select various events of interest. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 33 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 442 ++++++++++++++++++++- 2 files changed, 474 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 0f579eb24631..9caf70382088 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -87,3 +87,36 @@ KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/reset +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (W) Cancels all configuration on a trace unit and set it back + to its boot configuration. + +What: /sys/bus/coresight/devices/<memory_map>.etm/mode +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls various modes supported by this ETM, for example + P0 instruction tracing, branch broadcast, cycle counting and + context ID tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/pe +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls which PE to trace. + +What: /sys/bus/coresight/devices/<memory_map>.etm/event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. + +What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls the behavior of the events in bank 0 to 3. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index c7421f319350..1a93b968ab6e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -268,6 +268,46 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude) +{ + u8 idx = drvdata->addr_idx; + + /* + * TRCACATRn.TYPE bit[1:0]: type of comparison + * the trace unit performs + */ + if (BMVAL(drvdata->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) { + if (idx % 2 != 0) + return -EINVAL; + + /* + * We are performing instruction address comparison. Set the + * relevant bit of ViewInst Include/Exclude Control register + * for corresponding address comparator pair. + */ + if (drvdata->addr_type[idx] != ETM_ADDR_TYPE_RANGE || + drvdata->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE) + return -EINVAL; + + if (exclude == true) { + /* + * Set exclude bit and unset the include bit + * corresponding to comparator pair + */ + drvdata->viiectlr |= BIT(idx / 2 + 16); + drvdata->viiectlr &= ~BIT(idx / 2); + } else { + /* + * Set include bit and unset exclude bit + * corresponding to comparator pair + */ + drvdata->viiectlr |= BIT(idx / 2); + drvdata->viiectlr &= ~BIT(idx / 2 + 16); + } + } + return 0; +} + static ssize_t nr_pe_cmp_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -376,6 +416,402 @@ static ssize_t nr_ss_cmp_show(struct device *dev, } static DEVICE_ATTR_RO(nr_ss_cmp); +static ssize_t reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int i; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->mode = 0x0; + + /* Disable data tracing: do not trace load and store data transfers */ + drvdata->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE); + drvdata->cfg &= ~(BIT(1) | BIT(2)); + + /* Disable data value and data address tracing */ + drvdata->mode &= ~(ETM_MODE_DATA_TRACE_ADDR | + ETM_MODE_DATA_TRACE_VAL); + drvdata->cfg &= ~(BIT(16) | BIT(17)); + + /* Disable all events tracing */ + drvdata->eventctrl0 = 0x0; + drvdata->eventctrl1 = 0x0; + + /* Disable timestamp event */ + drvdata->ts_ctrl = 0x0; + + /* Disable stalling */ + drvdata->stall_ctrl = 0x0; + + /* Reset trace synchronization period to 2^8 = 256 bytes*/ + if (drvdata->syncpr == false) + drvdata->syncfreq = 0x8; + + /* + * Enable ViewInst to trace everything with start-stop logic in + * started state. ARM recommends start-stop logic is set before + * each trace run. + */ + drvdata->vinst_ctrl |= BIT(0); + if (drvdata->nr_addr_cmp == true) { + drvdata->mode |= ETM_MODE_VIEWINST_STARTSTOP; + /* SSSTATUS, bit[9] */ + drvdata->vinst_ctrl |= BIT(9); + } + + /* No address range filtering for ViewInst */ + drvdata->viiectlr = 0x0; + + /* No start-stop filtering for ViewInst */ + drvdata->vissctlr = 0x0; + + /* Disable seq events */ + for (i = 0; i < drvdata->nrseqstate-1; i++) + drvdata->seq_ctrl[i] = 0x0; + drvdata->seq_rst = 0x0; + drvdata->seq_state = 0x0; + + /* Disable external input events */ + drvdata->ext_inp = 0x0; + + drvdata->cntr_idx = 0x0; + for (i = 0; i < drvdata->nr_cntr; i++) { + drvdata->cntrldvr[i] = 0x0; + drvdata->cntr_ctrl[i] = 0x0; + drvdata->cntr_val[i] = 0x0; + } + + drvdata->res_idx = 0x0; + for (i = 0; i < drvdata->nr_resource; i++) + drvdata->res_ctrl[i] = 0x0; + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->ss_ctrl[i] = 0x0; + drvdata->ss_pe_cmp[i] = 0x0; + } + + drvdata->addr_idx = 0x0; + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + drvdata->addr_val[i] = 0x0; + drvdata->addr_acc[i] = 0x0; + drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE; + } + + drvdata->ctxid_idx = 0x0; + for (i = 0; i < drvdata->numcidc; i++) + drvdata->ctxid_val[i] = 0x0; + drvdata->ctxid_mask0 = 0x0; + drvdata->ctxid_mask1 = 0x0; + + drvdata->vmid_idx = 0x0; + for (i = 0; i < drvdata->numvmidc; i++) + drvdata->vmid_val[i] = 0x0; + drvdata->vmid_mask0 = 0x0; + drvdata->vmid_mask1 = 0x0; + + drvdata->trcid = drvdata->cpu + 1; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_WO(reset); + +static ssize_t mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->mode; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val, mode; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->mode = val & ETMv4_MODE_ALL; + + if (drvdata->mode & ETM_MODE_EXCLUDE) + etm4_set_mode_exclude(drvdata, true); + else + etm4_set_mode_exclude(drvdata, false); + + if (drvdata->instrp0 == true) { + /* start by clearing instruction P0 field */ + drvdata->cfg &= ~(BIT(1) | BIT(2)); + if (drvdata->mode & ETM_MODE_LOAD) + /* 0b01 Trace load instructions as P0 instructions */ + drvdata->cfg |= BIT(1); + if (drvdata->mode & ETM_MODE_STORE) + /* 0b10 Trace store instructions as P0 instructions */ + drvdata->cfg |= BIT(2); + if (drvdata->mode & ETM_MODE_LOAD_STORE) + /* + * 0b11 Trace load and store instructions + * as P0 instructions + */ + drvdata->cfg |= BIT(1) | BIT(2); + } + + /* bit[3], Branch broadcast mode */ + if ((drvdata->mode & ETM_MODE_BB) && (drvdata->trcbb == true)) + drvdata->cfg |= BIT(3); + else + drvdata->cfg &= ~BIT(3); + + /* bit[4], Cycle counting instruction trace bit */ + if ((drvdata->mode & ETMv4_MODE_CYCACC) && + (drvdata->trccci == true)) + drvdata->cfg |= BIT(4); + else + drvdata->cfg &= ~BIT(4); + + /* bit[6], Context ID tracing bit */ + if ((drvdata->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size)) + drvdata->cfg |= BIT(6); + else + drvdata->cfg &= ~BIT(6); + + if ((drvdata->mode & ETM_MODE_VMID) && (drvdata->vmid_size)) + drvdata->cfg |= BIT(7); + else + drvdata->cfg &= ~BIT(7); + + /* bits[10:8], Conditional instruction tracing bit */ + mode = ETM_MODE_COND(drvdata->mode); + if (drvdata->trccond == true) { + drvdata->cfg &= ~(BIT(8) | BIT(9) | BIT(10)); + drvdata->cfg |= mode << 8; + } + + /* bit[11], Global timestamp tracing bit */ + if ((drvdata->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size)) + drvdata->cfg |= BIT(11); + else + drvdata->cfg &= ~BIT(11); + + /* bit[12], Return stack enable bit */ + if ((drvdata->mode & ETM_MODE_RETURNSTACK) && + (drvdata->retstack == true)) + drvdata->cfg |= BIT(12); + else + drvdata->cfg &= ~BIT(12); + + /* bits[14:13], Q element enable field */ + mode = ETM_MODE_QELEM(drvdata->mode); + /* start by clearing QE bits */ + drvdata->cfg &= ~(BIT(13) | BIT(14)); + /* if supported, Q elements with instruction counts are enabled */ + if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) + drvdata->cfg |= BIT(13); + /* + * if supported, Q elements with and without instruction + * counts are enabled + */ + if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) + drvdata->cfg |= BIT(14); + + /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ + if ((drvdata->mode & ETM_MODE_ATB_TRIGGER) && + (drvdata->atbtrig == true)) + drvdata->eventctrl1 |= BIT(11); + else + drvdata->eventctrl1 &= ~BIT(11); + + /* bit[12], Low-power state behavior override bit */ + if ((drvdata->mode & ETM_MODE_LPOVERRIDE) && + (drvdata->lpoverride == true)) + drvdata->eventctrl1 |= BIT(12); + else + drvdata->eventctrl1 &= ~BIT(12); + + /* bit[8], Instruction stall bit */ + if (drvdata->mode & ETM_MODE_ISTALL_EN) + drvdata->stall_ctrl |= BIT(8); + else + drvdata->stall_ctrl &= ~BIT(8); + + /* bit[10], Prioritize instruction trace bit */ + if (drvdata->mode & ETM_MODE_INSTPRIO) + drvdata->stall_ctrl |= BIT(10); + else + drvdata->stall_ctrl &= ~BIT(10); + + /* bit[13], Trace overflow prevention bit */ + if ((drvdata->mode & ETM_MODE_NOOVERFLOW) && + (drvdata->nooverflow == true)) + drvdata->stall_ctrl |= BIT(13); + else + drvdata->stall_ctrl &= ~BIT(13); + + /* bit[9] Start/stop logic control bit */ + if (drvdata->mode & ETM_MODE_VIEWINST_STARTSTOP) + drvdata->vinst_ctrl |= BIT(9); + else + drvdata->vinst_ctrl &= ~BIT(9); + + /* bit[10], Whether a trace unit must trace a Reset exception */ + if (drvdata->mode & ETM_MODE_TRACE_RESET) + drvdata->vinst_ctrl |= BIT(10); + else + drvdata->vinst_ctrl &= ~BIT(10); + + /* bit[11], Whether a trace unit must trace a system error exception */ + if ((drvdata->mode & ETM_MODE_TRACE_ERR) && + (drvdata->trc_error == true)) + drvdata->vinst_ctrl |= BIT(11); + else + drvdata->vinst_ctrl &= ~BIT(11); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(mode); + +static ssize_t pe_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->pe_sel; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t pe_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val > drvdata->nr_pe) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + + drvdata->pe_sel = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(pe); + +static ssize_t event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->eventctrl0; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + switch (drvdata->nr_event) { + case 0x0: + /* EVENT0, bits[7:0] */ + drvdata->eventctrl0 = val & 0xFF; + break; + case 0x1: + /* EVENT1, bits[15:8] */ + drvdata->eventctrl0 = val & 0xFFFF; + break; + case 0x2: + /* EVENT2, bits[23:16] */ + drvdata->eventctrl0 = val & 0xFFFFFF; + break; + case 0x3: + /* EVENT3, bits[31:24] */ + drvdata->eventctrl0 = val; + break; + default: + break; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event); + +static ssize_t event_instren_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = BMVAL(drvdata->eventctrl1, 0, 3); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_instren_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* start by clearing all instruction event enable bits */ + drvdata->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); + switch (drvdata->nr_event) { + case 0x0: + /* generate Event element for event 1 */ + drvdata->eventctrl1 |= val & BIT(1); + break; + case 0x1: + /* generate Event element for event 1 and 2 */ + drvdata->eventctrl1 |= val & (BIT(0) | BIT(1)); + break; + case 0x2: + /* generate Event element for event 1, 2 and 3 */ + drvdata->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); + break; + case 0x3: + /* generate Event element for all 4 events */ + drvdata->eventctrl1 |= val & 0xF; + break; + default: + break; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event_instren); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -518,7 +954,6 @@ static ssize_t trcidr_show(struct device *dev, return ret; } static DEVICE_ATTR_RO(trcidr); - static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_nr_pe_cmp.attr, &dev_attr_nr_addr_cmp.attr, @@ -529,6 +964,11 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_nrseqstate.attr, &dev_attr_nr_resource.attr, &dev_attr_nr_ss_cmp.attr, + &dev_attr_reset.attr, + &dev_attr_mode.attr, + &dev_attr_pe.attr, + &dev_attr_event.attr, + &dev_attr_event_instren.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 04/11] coresight-etm4x: Controls pertaining to various configuration options 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 03/11] coresight-etm4x: Controls pertaining to the reset, mode, pe and events Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 05/11] coresight-etm4x: Controls pertaining to the ViewInst register Mathieu Poirier ` (5 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: mathieu.poirier, linux-api, linux-kernel, zhang.chunyan, linux-arm-kernel, kaixu.xia From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to configure: . global timestamp. . how often trace synchronisation occur. . the threashold value for cycle counting. . branch and broadcasting regions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 28 ++++- drivers/hwtracing/coresight/coresight-etm4x.c | 124 +++++++++++++++++++++ 2 files changed, 151 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 9caf70382088..2aeae2976c10 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -119,4 +119,30 @@ What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (RW) Controls the behavior of the events in bank 0 to 3. +Description: (RW) Controls the behavior of the events in bank 0 to 3 + +What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls the insertion of global timestamps in the trace + streams. + +What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls how often trace synchronization requests occur. + +What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Sets the threshold value for cycle counting. + +What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls which regions in the memory map are enabled to + use branch broadcasting. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 1a93b968ab6e..9812fbfdbeae 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -812,6 +812,126 @@ static ssize_t event_instren_store(struct device *dev, } static DEVICE_ATTR_RW(event_instren); +static ssize_t event_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ts_ctrl; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!drvdata->ts_size) + return -EINVAL; + + drvdata->ts_ctrl = val & ETMv4_EVENT_MASK; + return size; +} +static DEVICE_ATTR_RW(event_ts); + +static ssize_t syncfreq_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->syncfreq; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t syncfreq_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (drvdata->syncpr == true) + return -EINVAL; + + drvdata->syncfreq = val & ETMv4_SYNC_MASK; + return size; +} +static DEVICE_ATTR_RW(syncfreq); + +static ssize_t cyc_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ccctlr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cyc_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val < drvdata->ccitmin) + return -EINVAL; + + drvdata->ccctlr = val & ETM_CYC_THRESHOLD_MASK; + return size; +} +static DEVICE_ATTR_RW(cyc_threshold); + +static ssize_t bb_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->bb_ctrl; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t bb_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (drvdata->trcbb == false) + return -EINVAL; + if (!drvdata->nr_addr_cmp) + return -EINVAL; + /* + * Bit[7:0] selects which address range comparator is used for + * branch broadcast control. + */ + if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp) + return -EINVAL; + + drvdata->bb_ctrl = val; + return size; +} +static DEVICE_ATTR_RW(bb_ctrl); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -969,6 +1089,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_pe.attr, &dev_attr_event.attr, &dev_attr_event_instren.attr, + &dev_attr_event_ts.attr, + &dev_attr_syncfreq.attr, + &dev_attr_cyc_threshold.attr, + &dev_attr_bb_ctrl.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 05/11] coresight-etm4x: Controls pertaining to the ViewInst register 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 03/11] coresight-etm4x: Controls pertaining to the reset, mode, pe and events Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 04/11] coresight-etm4x: Controls pertaining to various configuration options Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 06/11] coresight-etm4x: Controls pertaining to the address comparator functions Mathieu Poirier ` (4 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan, mathieu.poirier From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to control the ViewInst register's event selector along with secure and non-secure exception level instruction tracing. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 98 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 2aeae2976c10..d7409c3d58e6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -146,3 +146,23 @@ KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. + +What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls instruction trace filtering. + +What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) In Secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. + +What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) In non-secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 9812fbfdbeae..4eb3babb4592 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -932,6 +932,101 @@ static ssize_t bb_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(bb_ctrl); +static ssize_t event_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->vinst_ctrl & ETMv4_EVENT_MASK; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + val &= ETMv4_EVENT_MASK; + drvdata->vinst_ctrl &= ~ETMv4_EVENT_MASK; + drvdata->vinst_ctrl |= val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event_vinst); + +static ssize_t s_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = BMVAL(drvdata->vinst_ctrl, 16, 19); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t s_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ + drvdata->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->s_ex_level; + drvdata->vinst_ctrl |= (val << 16); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(s_exlevel_vinst); + +static ssize_t ns_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* EXLEVEL_NS, bits[23:20] */ + val = BMVAL(drvdata->vinst_ctrl, 20, 23); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ns_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear EXLEVEL_NS bits (bit[23] is never implemented */ + drvdata->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->ns_ex_level; + drvdata->vinst_ctrl |= (val << 20); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ns_exlevel_vinst); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1093,6 +1188,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_syncfreq.attr, &dev_attr_cyc_threshold.attr, &dev_attr_bb_ctrl.attr, + &dev_attr_event_vinst.attr, + &dev_attr_s_exlevel_vinst.attr, + &dev_attr_ns_exlevel_vinst.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 06/11] coresight-etm4x: Controls pertaining to the address comparator functions 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier ` (2 preceding siblings ...) 2015-05-06 15:27 ` [PATCH v3 05/11] coresight-etm4x: Controls pertaining to the ViewInst register Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 07/11] coresight-etm4x: Controls pertaining to the sequencer functions Mathieu Poirier ` (3 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan, mathieu.poirier From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to control the various mode the address comparator registers can enact, i.e, start/top, single, and range. Also supplementing with address comparator types configuration registers access, mandatory to complete the configuration of the comparator functions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 423 +++++++++++++++++++++ 2 files changed, 448 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index d7409c3d58e6..8cdc4ad10bd6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -166,3 +166,28 @@ KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. + +What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Select which address comparator or pair (of comparators) to + work with. + +What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls what type of comparison the trace unit performs. + +What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Used to setup single address comparator values. + +What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Used to setup address range comparator values. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4eb3babb4592..6671be0036e2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1027,6 +1027,421 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, } static DEVICE_ATTR_RW(ns_exlevel_vinst); +static ssize_t addr_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->addr_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_addr_cmp * 2) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->addr_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_idx); + +static ssize_t addr_instdatatype_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t len; + u8 val, idx; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + val = BMVAL(drvdata->addr_acc[idx], 0, 1); + len = scnprintf(buf, PAGE_SIZE, "%s\n", + val == ETM_INSTR_ADDR ? "instr" : + (val == ETM_DATA_LOAD_ADDR ? "data_load" : + (val == ETM_DATA_STORE_ADDR ? "data_store" : + "data_load_store"))); + spin_unlock(&drvdata->spinlock); + return len; +} + +static ssize_t addr_instdatatype_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + char str[20] = ""; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (strlen(buf) >= 20) + return -EINVAL; + if (sscanf(buf, "%s", str) != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!strcmp(str, "instr")) + /* TYPE, bits[1:0] */ + drvdata->addr_acc[idx] &= ~(BIT(0) | BIT(1)); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_instdatatype); + +static ssize_t addr_single_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + idx = drvdata->addr_idx; + spin_lock(&drvdata->spinlock); + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_single_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_single); + +static ssize_t addr_range_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (idx % 2 != 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val1 = (unsigned long)drvdata->addr_val[idx]; + val2 = (unsigned long)drvdata->addr_val[idx + 1]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t addr_range_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + /* lower address comparator cannot have a higher address value */ + if (val1 > val2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (idx % 2 != 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val1; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_val[idx + 1] = (u64)val2; + drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE; + /* + * Program include or exclude control bits for vinst or vdata + * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE + */ + if (drvdata->mode & ETM_MODE_EXCLUDE) + etm4_set_mode_exclude(drvdata, true); + else + etm4_set_mode_exclude(drvdata, false); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_range); + +static ssize_t addr_start_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_start_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!drvdata->nr_addr_cmp) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_START; + drvdata->vissctlr |= BIT(idx); + /* SSSTATUS, bit[9] - turn on start/stop logic */ + drvdata->vinst_ctrl |= BIT(9); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_start); + +static ssize_t addr_stop_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_stop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!drvdata->nr_addr_cmp) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP; + drvdata->vissctlr |= BIT(idx + 16); + /* SSSTATUS, bit[9] - turn on start/stop logic */ + drvdata->vinst_ctrl |= BIT(9); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_stop); + +static ssize_t addr_ctxtype_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t len; + u8 idx, val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* CONTEXTTYPE, bits[3:2] */ + val = BMVAL(drvdata->addr_acc[idx], 2, 3); + len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" : + (val == ETM_CTX_CTXID ? "ctxid" : + (val == ETM_CTX_VMID ? "vmid" : "all"))); + spin_unlock(&drvdata->spinlock); + return len; +} + +static ssize_t addr_ctxtype_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + char str[10] = ""; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (strlen(buf) >= 10) + return -EINVAL; + if (sscanf(buf, "%s", str) != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!strcmp(str, "none")) + /* start by clearing context type bits */ + drvdata->addr_acc[idx] &= ~(BIT(2) | BIT(3)); + else if (!strcmp(str, "ctxid")) { + /* 0b01 The trace unit performs a Context ID */ + if (drvdata->numcidc) { + drvdata->addr_acc[idx] |= BIT(2); + drvdata->addr_acc[idx] &= ~BIT(3); + } + } else if (!strcmp(str, "vmid")) { + /* 0b10 The trace unit performs a VMID */ + if (drvdata->numvmidc) { + drvdata->addr_acc[idx] &= ~BIT(2); + drvdata->addr_acc[idx] |= BIT(3); + } + } else if (!strcmp(str, "all")) { + /* + * 0b11 The trace unit performs a Context ID + * comparison and a VMID + */ + if (drvdata->numcidc) + drvdata->addr_acc[idx] |= BIT(2); + if (drvdata->numvmidc) + drvdata->addr_acc[idx] |= BIT(3); + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_ctxtype); + +static ssize_t addr_context_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* context ID comparator bits[6:4] */ + val = BMVAL(drvdata->addr_acc[idx], 4, 6); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_context_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1)) + return -EINVAL; + if (val >= (drvdata->numcidc >= drvdata->numvmidc ? + drvdata->numcidc : drvdata->numvmidc)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* clear context ID comparator bits[6:4] */ + drvdata->addr_acc[idx] &= ~(BIT(4) | BIT(5) | BIT(6)); + drvdata->addr_acc[idx] |= (val << 4); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_context); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1191,6 +1606,14 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_event_vinst.attr, &dev_attr_s_exlevel_vinst.attr, &dev_attr_ns_exlevel_vinst.attr, + &dev_attr_addr_idx.attr, + &dev_attr_addr_instdatatype.attr, + &dev_attr_addr_single.attr, + &dev_attr_addr_range.attr, + &dev_attr_addr_start.attr, + &dev_attr_addr_stop.attr, + &dev_attr_addr_ctxtype.attr, + &dev_attr_addr_context.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 07/11] coresight-etm4x: Controls pertaining to the sequencer functions 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier ` (3 preceding siblings ...) 2015-05-06 15:27 ` [PATCH v3 06/11] coresight-etm4x: Controls pertaining to the address comparator functions Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> ` (2 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan, mathieu.poirier From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to access the sequencers related registers, more specifically the sequencer state, the sequencer state transition and the sequencer reset control registers. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 129 +++++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 8cdc4ad10bd6..44723f2e107e 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -191,3 +191,28 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup address range comparator values. + +What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Select which sequensor. + +What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Use this to set, or read, the sequencer state. + +What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Moves the sequencer state to a specific state. + +What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Moves the sequencer to state 0 when a programmed event + occurs. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 6671be0036e2..ca89e7ba4b75 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1442,6 +1442,131 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t seq_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nrseqstate - 1) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->seq_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(seq_idx); + +static ssize_t seq_state_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_state; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nrseqstate) + return -EINVAL; + + drvdata->seq_state = val; + return size; +} +static DEVICE_ATTR_RW(seq_state); + +static ssize_t seq_event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->seq_idx; + val = drvdata->seq_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->seq_idx; + /* RST, bits[7:0] */ + drvdata->seq_ctrl[idx] = val & 0xFF; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(seq_event); + +static ssize_t seq_reset_event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_rst; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_reset_event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!(drvdata->nrseqstate)) + return -EINVAL; + + drvdata->seq_rst = val & ETMv4_EVENT_MASK; + return size; +} +static DEVICE_ATTR_RW(seq_reset_event); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1614,6 +1739,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_seq_idx.attr, + &dev_attr_seq_state.attr, + &dev_attr_seq_event.attr, + &dev_attr_seq_reset_event.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> @ 2015-05-06 15:27 ` Mathieu Poirier [not found] ` <1430926047-9125-2-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2015-05-10 13:37 ` Greg KH 2015-05-06 15:27 ` [PATCH v3 02/11] coresight-etm4x: Controls pertaining to tracer configuration Mathieu Poirier ` (2 subsequent siblings) 3 siblings, 2 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-api-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kaixu.xia-QSEj5FYQhm4dnm+yROfE0A, zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A, mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A From: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block to support HW assisted tracing on ARMv7 and ARMv8 architectures. Signed-off-by: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Signed-off-by: Kaixu Xia <xiakaixu-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 28 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-etm4x.c | 825 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 391 ++++++++++ 5 files changed, 1256 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.h diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x new file mode 100644 index 000000000000..a4b623871ca0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -0,0 +1,28 @@ +What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Enable/disable tracing on this specific trace entiry. + Enabling a source implies the source has been configured + properly and a sink has been identidifed for it. The path + of coresight components linking the source to the sink is + configured and managed automatically by the coresight framework. + +What: /sys/bus/coresight/devices/<memory_map>.etm/status +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) List various control and status registers. The specific + layout and content is driver specific. + +What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Provides the current value of all the management registers. + +What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Provides value of all the ID registers (TRCIDRx). diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index fc1f1ae7a49d..8fac01eedee7 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -58,4 +58,15 @@ config CORESIGHT_SOURCE_ETM3X which allows tracing the instructions that a processor is executing This is primarily useful for instruction level tracing. Depending the ETM version data tracing may also be available. + +config CORESIGHT_SOURCE_ETM4X + bool "CoreSight Embedded Trace Macrocell 4.x driver" + depends on ARM64 + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for the ETM4.x tracer module, tracing the + instructions that a processor is executing. This is primarily useful + for instruction level tracing. Depending on the implemented version + data tracing may also be available. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4b4bec890ef5..0af28d43465c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o +obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c new file mode 100644 index 000000000000..db0bea4d4661 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -0,0 +1,825 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/smp.h> +#include <linux/sysfs.h> +#include <linux/stat.h> +#include <linux/clk.h> +#include <linux/cpu.h> +#include <linux/coresight.h> +#include <linux/pm_wakeup.h> +#include <linux/amba/bus.h> +#include <linux/seq_file.h> +#include <linux/uaccess.h> +#include <linux/pm_runtime.h> +#include <asm/sections.h> + +#include "coresight-etm4x.h" + +static int boot_enable; +module_param_named(boot_enable, boot_enable, int, S_IRUGO); + +/* The number of ETMv4 currently registered */ +static int etm4_count; +static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; + +static void etm4_os_unlock(void *info) +{ + struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info; + + /* Writing any value to ETMOSLAR unlocks the trace registers */ + writel_relaxed(0x0, drvdata->base + TRCOSLAR); + isb(); +} + +static bool etm4_arch_supported(u8 arch) +{ + switch (arch) { + case ETM_ARCH_V4: + break; + default: + return false; + } + return true; +} + +static int etm4_trace_id(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int trace_id = -1; + + if (!drvdata->enable) + return drvdata->trcid; + + pm_runtime_get_sync(drvdata->dev); + spin_lock_irqsave(&drvdata->spinlock, flags); + + CS_UNLOCK(drvdata->base); + trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR); + trace_id &= ETM_TRACEID_MASK; + CS_LOCK(drvdata->base); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + pm_runtime_put(drvdata->dev); + + return trace_id; +} + +static void etm4_enable_hw(void *info) +{ + int i; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + etm4_os_unlock(drvdata); + + /* Disable the trace unit before programming trace registers */ + writel_relaxed(0, drvdata->base + TRCPRGCTLR); + + /* wait for TRCSTATR.IDLE to go up */ + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) + dev_err(drvdata->dev, + "timeout observed when probing at offset %#x\n", + TRCSTATR); + + writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR); + writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR); + /* nothing specific implemented */ + writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); + writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R); + writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R); + writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR); + writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR); + writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR); + writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR); + writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR); + writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); + writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR); + writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR); + writel_relaxed(drvdata->vissctlr, + drvdata->base + TRCVISSCTLR); + writel_relaxed(drvdata->vipcssctlr, + drvdata->base + TRCVIPCSSCTLR); + for (i = 0; i < drvdata->nrseqstate - 1; i++) + writel_relaxed(drvdata->seq_ctrl[i], + drvdata->base + TRCSEQEVRn(i)); + writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR); + writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR); + writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR); + for (i = 0; i < drvdata->nr_cntr; i++) { + writel_relaxed(drvdata->cntrldvr[i], + drvdata->base + TRCCNTRLDVRn(i)); + writel_relaxed(drvdata->cntr_ctrl[i], + drvdata->base + TRCCNTCTLRn(i)); + writel_relaxed(drvdata->cntr_val[i], + drvdata->base + TRCCNTVRn(i)); + } + for (i = 0; i < drvdata->nr_resource; i++) + writel_relaxed(drvdata->res_ctrl[i], + drvdata->base + TRCRSCTLRn(i)); + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + writel_relaxed(drvdata->ss_ctrl[i], + drvdata->base + TRCSSCCRn(i)); + writel_relaxed(drvdata->ss_status[i], + drvdata->base + TRCSSCSRn(i)); + writel_relaxed(drvdata->ss_pe_cmp[i], + drvdata->base + TRCSSPCICRn(i)); + } + for (i = 0; i < drvdata->nr_addr_cmp; i++) { + writeq_relaxed(drvdata->addr_val[i], + drvdata->base + TRCACVRn(i)); + writeq_relaxed(drvdata->addr_acc[i], + drvdata->base + TRCACATRn(i)); + } + for (i = 0; i < drvdata->numcidc; i++) + writeq_relaxed(drvdata->ctxid_val[i], + drvdata->base + TRCCIDCVRn(i)); + writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); + writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); + + for (i = 0; i < drvdata->numvmidc; i++) + writeq_relaxed(drvdata->vmid_val[i], + drvdata->base + TRCVMIDCVRn(i)); + writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); + writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); + + /* Enable the trace unit */ + writel_relaxed(1, drvdata->base + TRCPRGCTLR); + + /* wait for TRCSTATR.IDLE to go back down to '0' */ + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) + dev_err(drvdata->dev, + "timeout observed when probing at offset %#x\n", + TRCSTATR); + + CS_LOCK(drvdata->base); + + dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); +} + +static int etm4_enable(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + pm_runtime_get_sync(drvdata->dev); + spin_lock(&drvdata->spinlock); + + /* + * Executing etm4_enable_hw on the cpu whose ETM is being enabled + * ensures that register writes occur when cpu is powered. + */ + ret = smp_call_function_single(drvdata->cpu, + etm4_enable_hw, drvdata, 1); + if (ret) + goto err; + drvdata->enable = true; + drvdata->sticky_enable = true; + + spin_unlock(&drvdata->spinlock); + + dev_info(drvdata->dev, "ETM tracing enabled\n"); + return 0; +err: + spin_unlock(&drvdata->spinlock); + pm_runtime_put(drvdata->dev); + return ret; +} + +static void etm4_disable_hw(void *info) +{ + u32 control; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + control = readl_relaxed(drvdata->base + TRCPRGCTLR); + + /* EN, bit[0] Trace unit enable bit */ + control &= ~0x1; + + /* make sure everything completes before disabling */ + mb(); + isb(); + writel_relaxed(control, drvdata->base + TRCPRGCTLR); + + CS_LOCK(drvdata->base); + + dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); +} + +static void etm4_disable(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* + * Taking hotplug lock here protects from clocks getting disabled + * with tracing being left on (crash scenario) if user disable occurs + * after cpu online mask indicates the cpu is offline but before the + * DYING hotplug callback is serviced by the ETM driver. + */ + get_online_cpus(); + spin_lock(&drvdata->spinlock); + + /* + * Executing etm4_disable_hw on the cpu whose ETM is being disabled + * ensures that register writes occur when cpu is powered. + */ + smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); + drvdata->enable = false; + + spin_unlock(&drvdata->spinlock); + put_online_cpus(); + + pm_runtime_put(drvdata->dev); + + dev_info(drvdata->dev, "ETM tracing disabled\n"); +} + +static const struct coresight_ops_source etm4_source_ops = { + .trace_id = etm4_trace_id, + .enable = etm4_enable, + .disable = etm4_disable, +}; + +static const struct coresight_ops etm4_cs_ops = { + .source_ops = &etm4_source_ops, +}; + +static ssize_t status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + unsigned long flags; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + pm_runtime_get_sync(drvdata->dev); + + spin_lock_irqsave(&drvdata->spinlock, flags); + CS_UNLOCK(drvdata->base); + ret = sprintf(buf, + "TRCCONFIGR:\t0x%08x\n" + "TRCEVENTCTL0R:\t0x%08x\n" + "TRCEVENTCTL1R:\t0x%08x\n" + "TRCSTALLCTLR:\t0x%08x\n" + "TRCSYNCPR:\t0x%08x\n" + "TRCTRACEIDR:\t0x%08x\n" + "TRCTSCTLR:\t0x%08x\n" + "TRCVDARCCTLR:\t0x%08x\n" + "TRCVDCTLR:\t0x%08x\n" + "TRCVDSACCTLR:\t0x%08x\n" + "TRCVICTLR:\t0x%08x\n" + "TRCVIIECTLR:\t0x%08x\n" + "TRCVISSCTLR:\t0x%08x\n" + "TRCPRGCTLR:\t0x%08x\n" + "CPU affinity:\t%d\n", + readl_relaxed(drvdata->base + TRCCONFIGR), + readl_relaxed(drvdata->base + TRCEVENTCTL0R), + readl_relaxed(drvdata->base + TRCEVENTCTL1R), + readl_relaxed(drvdata->base + TRCSTALLCTLR), + readl_relaxed(drvdata->base + TRCSYNCPR), + readl_relaxed(drvdata->base + TRCTRACEIDR), + readl_relaxed(drvdata->base + TRCTSCTLR), + readl_relaxed(drvdata->base + TRCVDARCCTLR), + readl_relaxed(drvdata->base + TRCVDCTLR), + readl_relaxed(drvdata->base + TRCVDSACCTLR), + readl_relaxed(drvdata->base + TRCVICTLR), + readl_relaxed(drvdata->base + TRCVIIECTLR), + readl_relaxed(drvdata->base + TRCVISSCTLR), + readl_relaxed(drvdata->base + TRCPRGCTLR), + drvdata->cpu); + CS_LOCK(drvdata->base); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + pm_runtime_put(drvdata->dev); + + return ret; +} +static DEVICE_ATTR_RO(status); + +static ssize_t mgmt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + unsigned long flags; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + pm_runtime_get_sync(drvdata->dev); + + spin_lock_irqsave(&drvdata->spinlock, flags); + CS_UNLOCK(drvdata->base); + ret = sprintf(buf, + "TRCOSLSR:\t0x%08x\n" + "TRCPDCR:\t0x%08x\n" + "TRCPDSR:\t0x%08x\n" + "TRCLSR:\t\t0x%08x\n" + "TRCAUTHSTATUS:\t0x%08x\n" + "TRCDEVID:\t0x%08x\n" + "TRCDEVTYPE:\t0x%08x\n" + "TRCPIDR0:\t0x%08x\n" + "TRCPIDR1:\t0x%08x\n" + "TRCPIDR2:\t0x%08x\n" + "TRCPIDR3:\t0x%08x\n", + readl_relaxed(drvdata->base + TRCOSLSR), + readl_relaxed(drvdata->base + TRCPDCR), + readl_relaxed(drvdata->base + TRCPDSR), + readl_relaxed(drvdata->base + TRCLSR), + readl_relaxed(drvdata->base + TRCAUTHSTATUS), + readl_relaxed(drvdata->base + TRCDEVID), + readl_relaxed(drvdata->base + TRCDEVTYPE), + readl_relaxed(drvdata->base + TRCPIDR0), + readl_relaxed(drvdata->base + TRCPIDR1), + readl_relaxed(drvdata->base + TRCPIDR2), + readl_relaxed(drvdata->base + TRCPIDR3)); + CS_LOCK(drvdata->base); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + pm_runtime_put(drvdata->dev); + + return ret; +} +static DEVICE_ATTR_RO(mgmt); + +static ssize_t trcidr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + unsigned long flags; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + pm_runtime_get_sync(drvdata->dev); + + spin_lock_irqsave(&drvdata->spinlock, flags); + CS_UNLOCK(drvdata->base); + ret = sprintf(buf, + "TRCIDR0:\t0x%08x\n" + "TRCIDR1:\t0x%08x\n" + "TRCIDR2:\t0x%08x\n" + "TRCIDR3:\t0x%08x\n" + "TRCIDR4:\t0x%08x\n" + "TRCIDR5:\t0x%08x\n" + "TRCIDR6:\t0x%08x\n" + "TRCIDR7:\t0x%08x\n" + "TRCIDR8:\t0x%08x\n" + "TRCIDR9:\t0x%08x\n" + "TRCIDR10:\t0x%08x\n" + "TRCIDR11:\t0x%08x\n" + "TRCIDR12:\t0x%08x\n" + "TRCIDR13:\t0x%08x\n", + readl_relaxed(drvdata->base + TRCIDR0), + readl_relaxed(drvdata->base + TRCIDR1), + readl_relaxed(drvdata->base + TRCIDR2), + readl_relaxed(drvdata->base + TRCIDR3), + readl_relaxed(drvdata->base + TRCIDR4), + readl_relaxed(drvdata->base + TRCIDR5), + readl_relaxed(drvdata->base + TRCIDR6), + readl_relaxed(drvdata->base + TRCIDR7), + readl_relaxed(drvdata->base + TRCIDR8), + readl_relaxed(drvdata->base + TRCIDR9), + readl_relaxed(drvdata->base + TRCIDR10), + readl_relaxed(drvdata->base + TRCIDR11), + readl_relaxed(drvdata->base + TRCIDR12), + readl_relaxed(drvdata->base + TRCIDR13)); + CS_LOCK(drvdata->base); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + pm_runtime_put(drvdata->dev); + + return ret; +} +static DEVICE_ATTR_RO(trcidr); + +static struct attribute *coresight_etmv4_attrs[] = { + &dev_attr_status.attr, + &dev_attr_mgmt.attr, + &dev_attr_trcidr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(coresight_etmv4); + +static void etm4_init_arch_data(void *info) +{ + u32 etmidr0; + u32 etmidr1; + u32 etmidr2; + u32 etmidr3; + u32 etmidr4; + u32 etmidr5; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + /* find all capabilities of the tracing unit */ + etmidr0 = readl_relaxed(drvdata->base + TRCIDR0); + + /* INSTP0, bits[2:1] P0 tracing support field */ + if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + drvdata->instrp0 = true; + else + drvdata->instrp0 = false; + + /* TRCBB, bit[5] Branch broadcast tracing support bit */ + if (BMVAL(etmidr0, 5, 5)) + drvdata->trcbb = true; + else + drvdata->trcbb = false; + + /* TRCCOND, bit[6] Conditional instruction tracing support bit */ + if (BMVAL(etmidr0, 6, 6)) + drvdata->trccond = true; + else + drvdata->trccond = false; + + /* TRCCCI, bit[7] Cycle counting instruction bit */ + if (BMVAL(etmidr0, 7, 7)) + drvdata->trccci = true; + else + drvdata->trccci = false; + + /* RETSTACK, bit[9] Return stack bit */ + if (BMVAL(etmidr0, 9, 9)) + drvdata->retstack = true; + else + drvdata->retstack = false; + + /* NUMEVENT, bits[11:10] Number of events field */ + drvdata->nr_event = BMVAL(etmidr0, 10, 11); + /* QSUPP, bits[16:15] Q element support field */ + drvdata->q_support = BMVAL(etmidr0, 15, 16); + /* TSSIZE, bits[28:24] Global timestamp size field */ + drvdata->ts_size = BMVAL(etmidr0, 24, 28); + + /* base architecture of trace unit */ + etmidr1 = readl_relaxed(drvdata->base + TRCIDR1); + /* + * TRCARCHMIN, bits[7:4] architecture the minor version number + * TRCARCHMAJ, bits[11:8] architecture major versin number + */ + drvdata->arch = BMVAL(etmidr1, 4, 11); + + /* maximum size of resources */ + etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); + /* CIDSIZE, bits[9:5] Indicates the Context ID size */ + drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); + /* VMIDSIZE, bits[14:10] Indicates the VMID size */ + drvdata->vmid_size = BMVAL(etmidr2, 10, 14); + /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ + drvdata->ccsize = BMVAL(etmidr2, 25, 28); + + etmidr3 = readl_relaxed(drvdata->base + TRCIDR3); + /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ + drvdata->ccitmin = BMVAL(etmidr3, 0, 11); + /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ + drvdata->s_ex_level = BMVAL(etmidr3, 16, 19); + /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ + drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23); + + /* + * TRCERR, bit[24] whether a trace unit can trace a + * system error exception. + */ + if (BMVAL(etmidr3, 24, 24)) + drvdata->trc_error = true; + else + drvdata->trc_error = false; + + /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ + if (BMVAL(etmidr3, 25, 25)) + drvdata->syncpr = true; + else + drvdata->syncpr = false; + + /* STALLCTL, bit[26] is stall control implemented? */ + if (BMVAL(etmidr3, 26, 26)) + drvdata->stallctl = true; + else + drvdata->stallctl = false; + + /* SYSSTALL, bit[27] implementation can support stall control? */ + if (BMVAL(etmidr3, 27, 27)) + drvdata->sysstall = true; + else + drvdata->sysstall = false; + + /* NUMPROC, bits[30:28] the number of PEs available for tracing */ + drvdata->nr_pe = BMVAL(etmidr3, 28, 30); + + /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ + if (BMVAL(etmidr3, 31, 31)) + drvdata->nooverflow = true; + else + drvdata->nooverflow = false; + + /* number of resources trace unit supports */ + etmidr4 = readl_relaxed(drvdata->base + TRCIDR4); + /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ + drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3); + /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ + drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15); + /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */ + drvdata->nr_resource = BMVAL(etmidr4, 16, 19); + /* + * NUMSSCC, bits[23:20] the number of single-shot + * comparator control for tracing + */ + drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); + /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ + drvdata->numcidc = BMVAL(etmidr4, 24, 27); + /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ + drvdata->numvmidc = BMVAL(etmidr4, 28, 31); + + etmidr5 = readl_relaxed(drvdata->base + TRCIDR5); + /* NUMEXTIN, bits[8:0] number of external inputs implemented */ + drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); + /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ + drvdata->trcid_size = BMVAL(etmidr5, 16, 21); + /* ATBTRIG, bit[22] implementation can support ATB triggers? */ + if (BMVAL(etmidr5, 22, 22)) + drvdata->atbtrig = true; + else + drvdata->atbtrig = false; + /* + * LPOVERRIDE, bit[23] implementation supports + * low-power state override + */ + if (BMVAL(etmidr5, 23, 23)) + drvdata->lpoverride = true; + else + drvdata->lpoverride = false; + /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ + drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); + /* NUMCNTR, bits[30:28] number of counters available for tracing */ + drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); + CS_LOCK(drvdata->base); +} + +static void etm4_init_default_data(struct etmv4_drvdata *drvdata) +{ + int i; + + drvdata->pe_sel = 0x0; + drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID | + ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK); + + /* disable all events tracing */ + drvdata->eventctrl0 = 0x0; + drvdata->eventctrl1 = 0x0; + + /* disable stalling */ + drvdata->stall_ctrl = 0x0; + + /* disable timestamp event */ + drvdata->ts_ctrl = 0x0; + + /* enable trace synchronization every 4096 bytes for trace */ + if (drvdata->syncpr == false) + drvdata->syncfreq = 0xC; + + /* + * enable viewInst to trace everything with start-stop logic in + * started state + */ + drvdata->vinst_ctrl |= BIT(0); + /* set initial state of start-stop logic */ + if (drvdata->nr_addr_cmp) + drvdata->vinst_ctrl |= BIT(9); + + /* no address range filtering for ViewInst */ + drvdata->viiectlr = 0x0; + /* no start-stop filtering for ViewInst */ + drvdata->vissctlr = 0x0; + + /* disable seq events */ + for (i = 0; i < drvdata->nrseqstate-1; i++) + drvdata->seq_ctrl[i] = 0x0; + drvdata->seq_rst = 0x0; + drvdata->seq_state = 0x0; + + /* disable external input events */ + drvdata->ext_inp = 0x0; + + for (i = 0; i < drvdata->nr_cntr; i++) { + drvdata->cntrldvr[i] = 0x0; + drvdata->cntr_ctrl[i] = 0x0; + drvdata->cntr_val[i] = 0x0; + } + + for (i = 2; i < drvdata->nr_resource * 2; i++) + drvdata->res_ctrl[i] = 0x0; + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->ss_ctrl[i] = 0x0; + drvdata->ss_pe_cmp[i] = 0x0; + } + + if (drvdata->nr_addr_cmp >= 1) { + drvdata->addr_val[0] = (unsigned long)_stext; + drvdata->addr_val[1] = (unsigned long)_etext; + drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE; + } + + for (i = 0; i < drvdata->numcidc; i++) + drvdata->ctxid_val[i] = 0x0; + drvdata->ctxid_mask0 = 0x0; + drvdata->ctxid_mask1 = 0x0; + + for (i = 0; i < drvdata->numvmidc; i++) + drvdata->vmid_val[i] = 0x0; + drvdata->vmid_mask0 = 0x0; + drvdata->vmid_mask1 = 0x0; + + /* + * A trace ID value of 0 is invalid, so let's start at some + * random value that fits in 7 bits. ETMv3.x has 0x10 so let's + * start at 0x20. + */ + drvdata->trcid = 0x20 + drvdata->cpu; +} + +static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + + if (!etmdrvdata[cpu]) + goto out; + + switch (action & (~CPU_TASKS_FROZEN)) { + case CPU_STARTING: + spin_lock(&etmdrvdata[cpu]->spinlock); + if (!etmdrvdata[cpu]->os_unlock) { + etm4_os_unlock(etmdrvdata[cpu]); + etmdrvdata[cpu]->os_unlock = true; + } + + if (etmdrvdata[cpu]->enable) + etm4_enable_hw(etmdrvdata[cpu]); + spin_unlock(&etmdrvdata[cpu]->spinlock); + break; + + case CPU_ONLINE: + if (etmdrvdata[cpu]->boot_enable && + !etmdrvdata[cpu]->sticky_enable) + coresight_enable(etmdrvdata[cpu]->csdev); + break; + + case CPU_DYING: + spin_lock(&etmdrvdata[cpu]->spinlock); + if (etmdrvdata[cpu]->enable) + etm4_disable_hw(etmdrvdata[cpu]); + spin_unlock(&etmdrvdata[cpu]->spinlock); + break; + } +out: + return NOTIFY_OK; +} + +static struct notifier_block etm4_cpu_notifier = { + .notifier_call = etm4_cpu_callback, +}; + +static int etm4_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata = NULL; + struct etmv4_drvdata *drvdata; + struct resource *res = &adev->res; + struct coresight_desc *desc; + struct device_node *np = adev->dev.of_node; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + } + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = pdata ? pdata->cpu : 0; + + get_online_cpus(); + etmdrvdata[drvdata->cpu] = drvdata; + + if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1)) + drvdata->os_unlock = true; + + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, drvdata, 1)) + dev_err(dev, "ETM arch init failed\n"); + + if (!etm4_count++) + register_hotcpu_notifier(&etm4_cpu_notifier); + + put_online_cpus(); + + if (etm4_arch_supported(drvdata->arch) == false) { + ret = -EINVAL; + goto err_arch_supported; + } + etm4_init_default_data(drvdata); + + pm_runtime_put(&adev->dev); + + desc->type = CORESIGHT_DEV_TYPE_SOURCE; + desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; + desc->ops = &etm4_cs_ops; + desc->pdata = pdata; + desc->dev = dev; + desc->groups = coresight_etmv4_groups; + drvdata->csdev = coresight_register(desc); + if (IS_ERR(drvdata->csdev)) { + ret = PTR_ERR(drvdata->csdev); + goto err_coresight_register; + } + + dev_info(dev, "%s initialized\n", (char *)id->data); + + if (boot_enable) { + coresight_enable(drvdata->csdev); + drvdata->boot_enable = true; + } + + return 0; + +err_arch_supported: + pm_runtime_put(&adev->dev); +err_coresight_register: + if (--etm4_count == 0) + unregister_hotcpu_notifier(&etm4_cpu_notifier); + return ret; +} + +static int etm4_remove(struct amba_device *adev) +{ + struct etmv4_drvdata *drvdata = amba_get_drvdata(adev); + + coresight_unregister(drvdata->csdev); + if (--etm4_count == 0) + unregister_hotcpu_notifier(&etm4_cpu_notifier); + + return 0; +} + +static struct amba_id etm4_ids[] = { + { /* ETM 4.0 - Juno board */ + .id = 0x000bb95e, + .mask = 0x000fffff, + .data = "ETM 4.0", + }, + { 0, 0}, +}; + +static struct amba_driver etm4x_driver = { + .drv = { + .name = "coresight-etm4x", + }, + .probe = etm4_probe, + .remove = etm4_remove, + .id_table = etm4_ids, +}; + +module_amba_driver(etm4x_driver); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h new file mode 100644 index 000000000000..e08e983dd2d9 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -0,0 +1,391 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CORESIGHT_CORESIGHT_ETM_H +#define _CORESIGHT_CORESIGHT_ETM_H + +#include <linux/spinlock.h> +#include "coresight-priv.h" + +/* + * Device registers: + * 0x000 - 0x2FC: Trace registers + * 0x300 - 0x314: Management registers + * 0x318 - 0xEFC: Trace registers + * 0xF00: Management registers + * 0xFA0 - 0xFA4: Trace registers + * 0xFA8 - 0xFFC: Management registers + */ +/* Trace registers (0x000-0x2FC) */ +/* Main control and configuration registers */ +#define TRCPRGCTLR 0x004 +#define TRCPROCSELR 0x008 +#define TRCSTATR 0x00C +#define TRCCONFIGR 0x010 +#define TRCAUXCTLR 0x018 +#define TRCEVENTCTL0R 0x020 +#define TRCEVENTCTL1R 0x024 +#define TRCSTALLCTLR 0x02C +#define TRCTSCTLR 0x030 +#define TRCSYNCPR 0x034 +#define TRCCCCTLR 0x038 +#define TRCBBCTLR 0x03C +#define TRCTRACEIDR 0x040 +#define TRCQCTLR 0x044 +/* Filtering control registers */ +#define TRCVICTLR 0x080 +#define TRCVIIECTLR 0x084 +#define TRCVISSCTLR 0x088 +#define TRCVIPCSSCTLR 0x08C +#define TRCVDCTLR 0x0A0 +#define TRCVDSACCTLR 0x0A4 +#define TRCVDARCCTLR 0x0A8 +/* Derived resources registers */ +#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQRSTEVR 0x118 +#define TRCSEQSTR 0x11C +#define TRCEXTINSELR 0x120 +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) +#define TRCCNTVRn(n) (0x160 + (n * 4)) +/* ID registers */ +#define TRCIDR8 0x180 +#define TRCIDR9 0x184 +#define TRCIDR10 0x188 +#define TRCIDR11 0x18C +#define TRCIDR12 0x190 +#define TRCIDR13 0x194 +#define TRCIMSPEC0 0x1C0 +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIDR0 0x1E0 +#define TRCIDR1 0x1E4 +#define TRCIDR2 0x1E8 +#define TRCIDR3 0x1EC +#define TRCIDR4 0x1F0 +#define TRCIDR5 0x1F4 +#define TRCIDR6 0x1F8 +#define TRCIDR7 0x1FC +/* Resource selection registers */ +#define TRCRSCTLRn(n) (0x200 + (n * 4)) +/* Single-shot comparator registers */ +#define TRCSSCCRn(n) (0x280 + (n * 4)) +#define TRCSSCSRn(n) (0x2A0 + (n * 4)) +#define TRCSSPCICRn(n) (0x2C0 + (n * 4)) +/* Management registers (0x300-0x314) */ +#define TRCOSLAR 0x300 +#define TRCOSLSR 0x304 +#define TRCPDCR 0x310 +#define TRCPDSR 0x314 +/* Trace registers (0x318-0xEFC) */ +/* Comparator registers */ +#define TRCACVRn(n) (0x400 + (n * 8)) +#define TRCACATRn(n) (0x480 + (n * 8)) +#define TRCDVCVRn(n) (0x500 + (n * 16)) +#define TRCDVCMRn(n) (0x580 + (n * 16)) +#define TRCCIDCVRn(n) (0x600 + (n * 8)) +#define TRCVMIDCVRn(n) (0x640 + (n * 8)) +#define TRCCIDCCTLR0 0x680 +#define TRCCIDCCTLR1 0x684 +#define TRCVMIDCCTLR0 0x688 +#define TRCVMIDCCTLR1 0x68C +/* Management register (0xF00) */ +/* Integration control registers */ +#define TRCITCTRL 0xF00 +/* Trace registers (0xFA0-0xFA4) */ +/* Claim tag registers */ +#define TRCCLAIMSET 0xFA0 +#define TRCCLAIMCLR 0xFA4 +/* Management registers (0xFA8-0xFFC) */ +#define TRCDEVAFF0 0xFA8 +#define TRCDEVAFF1 0xFAC +#define TRCLAR 0xFB0 +#define TRCLSR 0xFB4 +#define TRCAUTHSTATUS 0xFB8 +#define TRCDEVARCH 0xFBC +#define TRCDEVID 0xFC8 +#define TRCDEVTYPE 0xFCC +#define TRCPIDR4 0xFD0 +#define TRCPIDR5 0xFD4 +#define TRCPIDR6 0xFD8 +#define TRCPIDR7 0xFDC +#define TRCPIDR0 0xFE0 +#define TRCPIDR1 0xFE4 +#define TRCPIDR2 0xFE8 +#define TRCPIDR3 0xFEC +#define TRCCIDR0 0xFF0 +#define TRCCIDR1 0xFF4 +#define TRCCIDR2 0xFF8 +#define TRCCIDR3 0xFFC + +/* ETMv4 resources */ +#define ETM_MAX_NR_PE 8 +#define ETMv4_MAX_CNTR 4 +#define ETM_MAX_SEQ_STATES 4 +#define ETM_MAX_EXT_INP_SEL 4 +#define ETM_MAX_EXT_INP 256 +#define ETM_MAX_EXT_OUT 4 +#define ETM_MAX_SINGLE_ADDR_CMP 16 +#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) +#define ETM_MAX_DATA_VAL_CMP 8 +#define ETMv4_MAX_CTXID_CMP 8 +#define ETM_MAX_VMID_CMP 8 +#define ETM_MAX_PE_CMP 8 +#define ETM_MAX_RES_SEL 16 +#define ETM_MAX_SS_CMP 8 + +#define ETM_ARCH_V4 0x40 +#define ETMv4_SYNC_MASK 0x1F +#define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETMv4_EVENT_MASK 0xFF +#define ETM_CNTR_MAX_VAL 0xFFFF +#define ETM_TRACEID_MASK 0x3f + +/* ETMv4 programming modes */ +#define ETM_MODE_EXCLUDE BIT(0) +#define ETM_MODE_LOAD BIT(1) +#define ETM_MODE_STORE BIT(2) +#define ETM_MODE_LOAD_STORE BIT(3) +#define ETM_MODE_BB BIT(4) +#define ETMv4_MODE_CYCACC BIT(5) +#define ETMv4_MODE_CTXID BIT(6) +#define ETM_MODE_VMID BIT(7) +#define ETM_MODE_COND(val) BMVAL(val, 8, 10) +#define ETMv4_MODE_TIMESTAMP BIT(11) +#define ETM_MODE_RETURNSTACK BIT(12) +#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) +#define ETM_MODE_DATA_TRACE_ADDR BIT(15) +#define ETM_MODE_DATA_TRACE_VAL BIT(16) +#define ETM_MODE_ISTALL BIT(17) +#define ETM_MODE_DSTALL BIT(18) +#define ETM_MODE_ATB_TRIGGER BIT(19) +#define ETM_MODE_LPOVERRIDE BIT(20) +#define ETM_MODE_ISTALL_EN BIT(21) +#define ETM_MODE_DSTALL_EN BIT(22) +#define ETM_MODE_INSTPRIO BIT(23) +#define ETM_MODE_NOOVERFLOW BIT(24) +#define ETM_MODE_TRACE_RESET BIT(25) +#define ETM_MODE_TRACE_ERR BIT(26) +#define ETM_MODE_VIEWINST_STARTSTOP BIT(27) +#define ETMv4_MODE_ALL 0xFFFFFFF + +#define TRCSTATR_IDLE_BIT 0 + +/** + * struct etm4_drvdata - specifics associated to an ETM component + * @base: Memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: Component vitals needed by the framework. + * @spinlock: Only one at a time pls. + * @cpu: The cpu this component is affined to. + * @arch: ETM version number. + * @enable: Is this ETM currently tracing. + * @sticky_enable: true if ETM base configuration has been done. + * @boot_enable:True if we should start tracing at boot time. + * @os_unlock: True if access to management registers is allowed. + * @nr_pe: The number of processing entity available for tracing. + * @nr_pe_cmp: The number of processing entity comparator inputs that are + * available for tracing. + * @nr_addr_cmp:Number of pairs of address comparators available + * as found in ETMIDR4 0-3. + * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. + * @nr_ext_inp: Number of external input. + * @numcidc: Number of contextID comparators. + * @numvmidc: Number of VMID comparators. + * @nrseqstate: The number of sequencer states that are implemented. + * @nr_event: Indicates how many events the trace unit support. + * @nr_resource:The number of resource selection pairs available for tracing. + * @nr_ss_cmp: Number of single-shot comparator controls that are available. + * @mode: Controls various modes supported by this ETM. + * @trcid: value of the current ID for this component. + * @trcid_size: Indicates the trace ID width. + * @instrp0: Tracing of load and store instructions + * as P0 elements is supported. + * @trccond: If the trace unit supports conditional + * instruction tracing. + * @retstack: Indicates if the implementation supports a return stack. + * @trc_error: Whether a trace unit can trace a system + * error exception. + * @atbtrig: If the implementation can support ATB triggers + * @lpoverride: If the implementation can support low-power state over. + * @pe_sel: Controls which PE to trace. + * @cfg: Controls the tracing options. + * @eventctrl0: Controls the tracing of arbitrary events. + * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. + * @stallctl: If functionality that prevents trace unit buffer overflows + * is available. + * @sysstall: Does the system support stall control of the PE? + * @nooverflow: Indicate if overflow prevention is supported. + * @stall_ctrl: Enables trace unit functionality that prevents trace + * unit buffer overflows. + * @ts_size: Global timestamp size field. + * @ts_ctrl: Controls the insertion of global timestamps in the + * trace streams. + * @syncpr: Indicates if an implementation has a fixed + * synchronization period. + * @syncfreq: Controls how often trace synchronization requests occur. + * @trccci: Indicates if the trace unit supports cycle counting + * for instruction. + * @ccsize: Indicates the size of the cycle counter in bits. + * @ccitmin: minimum value that can be programmed in + * the TRCCCCTLR register. + * @ccctlr: Sets the threshold value for cycle counting. + * @trcbb: Indicates if the trace unit supports branch broadcast tracing. + * @q_support: Q element support characteristics. + * @vinst_ctrl: Controls instruction trace filtering. + * @viiectlr: Set or read, the address range comparators. + * @vissctlr: Set, or read, the single address comparators that control the + * ViewInst start-stop logic. + * @vipcssctlr: Set, or read, which PE comparator inputs can control the + * ViewInst start-stop logic. + * @seq_idx: Sequencor index selector. + * @seq_ctrl: Control for the sequencer state transition control register. + * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. + * @seq_state: Set, or read the sequencer state. + * @cntr_idx: Counter index seletor. + * @cntrldvr: Sets or returns the reload count value for a counter. + * @cntr_ctrl: Controls the operation of a counter. + * @cntr_val: Sets or returns the value for a counter. + * @res_idx: Resource index selector. + * @res_ctrl: Controls the selection of the resources in the trace unit. + * @ss_ctrl: Controls the corresponding single-shot comparator resource. + * @ss_status: The status of the corresponding single-shot comparator. + * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. + * @addr_idx: Address comparator index selector. + * @addr_val: Value for address comparator. + * @addr_acc: Address comparator access type. + * @addr_type: Current status of the comparator register. + * @ctxid_idx: Context ID index selector. + * @ctxid_size: Size of the context ID field to consider. + * @ctxid_val: Value of the context ID comparator. + * @ctxid_mask0:Context ID comparator mask for comparator 0-3. + * @ctxid_mask1:Context ID comparator mask for comparator 4-7. + * @vmid_idx: VM ID index selector. + * @vmid_size: Size of the VM ID comparator to consider. + * @vmid_val: Value of the VM ID comparator. + * @vmid_mask0: VM ID comparator mask for comparator 0-3. + * @vmid_mask1: VM ID comparator mask for comparator 4-7. + * @s_ex_level: In secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ns_ex_level:In non-secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ext_inp: External input selection. + */ +struct etmv4_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + int cpu; + u8 arch; + bool enable; + bool sticky_enable; + bool boot_enable; + bool os_unlock; + u8 nr_pe; + u8 nr_pe_cmp; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 numcidc; + u8 numvmidc; + u8 nrseqstate; + u8 nr_event; + u8 nr_resource; + u8 nr_ss_cmp; + u32 mode; + u8 trcid; + u8 trcid_size; + bool instrp0; + bool trccond; + bool retstack; + bool trc_error; + bool atbtrig; + bool lpoverride; + u32 pe_sel; + u32 cfg; + u32 eventctrl0; + u32 eventctrl1; + bool stallctl; + bool sysstall; + bool nooverflow; + u32 stall_ctrl; + u8 ts_size; + u32 ts_ctrl; + bool syncpr; + u32 syncfreq; + bool trccci; + u8 ccsize; + u8 ccitmin; + u32 ccctlr; + bool trcbb; + u32 bb_ctrl; + bool q_support; + u32 vinst_ctrl; + u32 viiectlr; + u32 vissctlr; + u32 vipcssctlr; + u8 seq_idx; + u32 seq_ctrl[ETM_MAX_SEQ_STATES]; + u32 seq_rst; + u32 seq_state; + u8 cntr_idx; + u32 cntrldvr[ETMv4_MAX_CNTR]; + u32 cntr_ctrl[ETMv4_MAX_CNTR]; + u32 cntr_val[ETMv4_MAX_CNTR]; + u8 res_idx; + u32 res_ctrl[ETM_MAX_RES_SEL]; + u32 ss_ctrl[ETM_MAX_SS_CMP]; + u32 ss_status[ETM_MAX_SS_CMP]; + u32 ss_pe_cmp[ETM_MAX_SS_CMP]; + u8 addr_idx; + u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; + u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; + u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; + u8 ctxid_idx; + u8 ctxid_size; + u64 ctxid_val[ETMv4_MAX_CTXID_CMP]; + u32 ctxid_mask0; + u32 ctxid_mask1; + u8 vmid_idx; + u8 vmid_size; + u64 vmid_val[ETM_MAX_VMID_CMP]; + u32 vmid_mask0; + u32 vmid_mask1; + u8 s_ex_level; + u8 ns_ex_level; + u32 ext_inp; +}; + +/* Address comparator access types */ +enum etm_addr_acctype { + ETM_INSTR_ADDR, + ETM_DATA_LOAD_ADDR, + ETM_DATA_STORE_ADDR, + ETM_DATA_LOAD_STORE_ADDR, +}; + +/* Address comparator context types */ +enum etm_addr_ctxtype { + ETM_CTX_NONE, + ETM_CTX_CTXID, + ETM_CTX_VMID, + ETM_CTX_CTXID_VMID, +}; + +enum etm_addr_type { + ETM_ADDR_TYPE_NONE, + ETM_ADDR_TYPE_SINGLE, + ETM_ADDR_TYPE_RANGE, + ETM_ADDR_TYPE_START, + ETM_ADDR_TYPE_STOP, +}; +#endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1430926047-9125-2-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* Re: [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver [not found] ` <1430926047-9125-2-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> @ 2015-05-08 8:27 ` Ivan T. Ivanov 2015-05-08 13:12 ` Mathieu Poirier 0 siblings, 1 reply; 15+ messages in thread From: Ivan T. Ivanov @ 2015-05-08 8:27 UTC (permalink / raw) To: Mathieu Poirier Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-api-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kaixu.xia-QSEj5FYQhm4dnm+yROfE0A, zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A Hi Mathieu, On Wed, 2015-05-06 at 09:27 -0600, Mathieu Poirier wrote: > > +static struct amba_id etm4_ids[] = { > + { /* ETM 4.0 - Juno board */ > + .id = 0x000bb95e, > + .mask = 0x000fffff, > + .data = "ETM 4.0", > + }, > + { 0, 0}, > +}; > + > Any particular reason to remove device ID for the Hi6220 board? It happens to be the same ID used in Qualcomm 8x16 ETM components. Regards, Ivan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver 2015-05-08 8:27 ` Ivan T. Ivanov @ 2015-05-08 13:12 ` Mathieu Poirier 0 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-08 13:12 UTC (permalink / raw) To: Ivan T. Ivanov Cc: Greg KH, linux-arm-kernel@lists.infradead.org, linux-api, linux-kernel@vger.kernel.org, Kaixu Xia, Chunyan Zhang On 8 May 2015 at 02:27, Ivan T. Ivanov <iivanov@mm-sol.com> wrote: > > Hi Mathieu, > > On Wed, 2015-05-06 at 09:27 -0600, Mathieu Poirier wrote: >> >> +static struct amba_id etm4_ids[] = { >> + { /* ETM 4.0 - Juno board */ >> + .id = 0x000bb95e, >> + .mask = 0x000fffff, >> + .data = "ETM 4.0", >> + }, >> + { 0, 0}, >> +}; >> + >> > > Any particular reason to remove device ID for the > Hi6220 board? It happens to be the same ID used in > Qualcomm 8x16 ETM components. Efforts to push support for the Hi6220 board upstream have been abandoned, hence the decision to remove the entry. Apologies for the inconvenience, I will add it back. Mathieu > > Regards, > Ivan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver 2015-05-06 15:27 ` [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver Mathieu Poirier [not found] ` <1430926047-9125-2-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> @ 2015-05-10 13:37 ` Greg KH 1 sibling, 0 replies; 15+ messages in thread From: Greg KH @ 2015-05-10 13:37 UTC (permalink / raw) To: Mathieu Poirier Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan On Wed, May 06, 2015 at 09:27:17AM -0600, Mathieu Poirier wrote: > From: Pratik Patel <pratikp@codeaurora.org> > > This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block > to support HW assisted tracing on ARMv7 and ARMv8 architectures. > > Signed-off-by: Pratik Patel <pratikp@codeaurora.org> > Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> > --- > .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 28 + > drivers/hwtracing/coresight/Kconfig | 11 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-etm4x.c | 825 +++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-etm4x.h | 391 ++++++++++ > 5 files changed, 1256 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.c > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.h > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > new file mode 100644 > index 000000000000..a4b623871ca0 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > @@ -0,0 +1,28 @@ > +What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source > +Date: April 2015 > +KernelVersion: 4.01 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Enable/disable tracing on this specific trace entiry. > + Enabling a source implies the source has been configured > + properly and a sink has been identidifed for it. The path > + of coresight components linking the source to the sink is > + configured and managed automatically by the coresight framework. > + > +What: /sys/bus/coresight/devices/<memory_map>.etm/status > +Date: April 2015 > +KernelVersion: 4.01 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) List various control and status registers. The specific > + layout and content is driver specific. > + > +What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt > +Date: April 2015 > +KernelVersion: 4.01 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Provides the current value of all the management registers. > + > +What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr > +Date: April 2015 > +KernelVersion: 4.01 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Provides value of all the ID registers (TRCIDRx). > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index fc1f1ae7a49d..8fac01eedee7 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -58,4 +58,15 @@ config CORESIGHT_SOURCE_ETM3X > which allows tracing the instructions that a processor is executing > This is primarily useful for instruction level tracing. Depending > the ETM version data tracing may also be available. > + > +config CORESIGHT_SOURCE_ETM4X > + bool "CoreSight Embedded Trace Macrocell 4.x driver" > + depends on ARM64 > + select CORESIGHT_LINKS_AND_SINKS > + help > + This driver provides support for the ETM4.x tracer module, tracing the > + instructions that a processor is executing. This is primarily useful > + for instruction level tracing. Depending on the implemented version > + data tracing may also be available. > + > endif > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 4b4bec890ef5..0af28d43465c 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -9,3 +9,4 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o > obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ > coresight-replicator.o > obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o > +obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > new file mode 100644 > index 000000000000..db0bea4d4661 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -0,0 +1,825 @@ > +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/kernel.h> > +#include <linux/moduleparam.h> > +#include <linux/init.h> > +#include <linux/types.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/err.h> > +#include <linux/fs.h> > +#include <linux/slab.h> > +#include <linux/delay.h> > +#include <linux/smp.h> > +#include <linux/sysfs.h> > +#include <linux/stat.h> > +#include <linux/clk.h> > +#include <linux/cpu.h> > +#include <linux/coresight.h> > +#include <linux/pm_wakeup.h> > +#include <linux/amba/bus.h> > +#include <linux/seq_file.h> > +#include <linux/uaccess.h> > +#include <linux/pm_runtime.h> > +#include <asm/sections.h> > + > +#include "coresight-etm4x.h" > + > +static int boot_enable; > +module_param_named(boot_enable, boot_enable, int, S_IRUGO); > + > +/* The number of ETMv4 currently registered */ > +static int etm4_count; > +static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; > + > +static void etm4_os_unlock(void *info) > +{ > + struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info; > + > + /* Writing any value to ETMOSLAR unlocks the trace registers */ > + writel_relaxed(0x0, drvdata->base + TRCOSLAR); > + isb(); > +} > + > +static bool etm4_arch_supported(u8 arch) > +{ > + switch (arch) { > + case ETM_ARCH_V4: > + break; > + default: > + return false; > + } > + return true; > +} > + > +static int etm4_trace_id(struct coresight_device *csdev) > +{ > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + unsigned long flags; > + int trace_id = -1; > + > + if (!drvdata->enable) > + return drvdata->trcid; > + > + pm_runtime_get_sync(drvdata->dev); > + spin_lock_irqsave(&drvdata->spinlock, flags); > + > + CS_UNLOCK(drvdata->base); > + trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR); > + trace_id &= ETM_TRACEID_MASK; > + CS_LOCK(drvdata->base); > + > + spin_unlock_irqrestore(&drvdata->spinlock, flags); > + pm_runtime_put(drvdata->dev); > + > + return trace_id; > +} > + > +static void etm4_enable_hw(void *info) > +{ > + int i; > + struct etmv4_drvdata *drvdata = info; > + > + CS_UNLOCK(drvdata->base); > + > + etm4_os_unlock(drvdata); > + > + /* Disable the trace unit before programming trace registers */ > + writel_relaxed(0, drvdata->base + TRCPRGCTLR); > + > + /* wait for TRCSTATR.IDLE to go up */ > + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) > + dev_err(drvdata->dev, > + "timeout observed when probing at offset %#x\n", > + TRCSTATR); > + > + writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR); > + writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR); > + /* nothing specific implemented */ > + writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); > + writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R); > + writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R); > + writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR); > + writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR); > + writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR); > + writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR); > + writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR); > + writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); > + writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR); > + writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR); > + writel_relaxed(drvdata->vissctlr, > + drvdata->base + TRCVISSCTLR); > + writel_relaxed(drvdata->vipcssctlr, > + drvdata->base + TRCVIPCSSCTLR); > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + writel_relaxed(drvdata->seq_ctrl[i], > + drvdata->base + TRCSEQEVRn(i)); > + writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR); > + writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR); > + writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR); > + for (i = 0; i < drvdata->nr_cntr; i++) { > + writel_relaxed(drvdata->cntrldvr[i], > + drvdata->base + TRCCNTRLDVRn(i)); > + writel_relaxed(drvdata->cntr_ctrl[i], > + drvdata->base + TRCCNTCTLRn(i)); > + writel_relaxed(drvdata->cntr_val[i], > + drvdata->base + TRCCNTVRn(i)); > + } > + for (i = 0; i < drvdata->nr_resource; i++) > + writel_relaxed(drvdata->res_ctrl[i], > + drvdata->base + TRCRSCTLRn(i)); > + > + for (i = 0; i < drvdata->nr_ss_cmp; i++) { > + writel_relaxed(drvdata->ss_ctrl[i], > + drvdata->base + TRCSSCCRn(i)); > + writel_relaxed(drvdata->ss_status[i], > + drvdata->base + TRCSSCSRn(i)); > + writel_relaxed(drvdata->ss_pe_cmp[i], > + drvdata->base + TRCSSPCICRn(i)); > + } > + for (i = 0; i < drvdata->nr_addr_cmp; i++) { > + writeq_relaxed(drvdata->addr_val[i], > + drvdata->base + TRCACVRn(i)); > + writeq_relaxed(drvdata->addr_acc[i], > + drvdata->base + TRCACATRn(i)); > + } > + for (i = 0; i < drvdata->numcidc; i++) > + writeq_relaxed(drvdata->ctxid_val[i], > + drvdata->base + TRCCIDCVRn(i)); > + writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); > + writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); > + > + for (i = 0; i < drvdata->numvmidc; i++) > + writeq_relaxed(drvdata->vmid_val[i], > + drvdata->base + TRCVMIDCVRn(i)); > + writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); > + writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); > + > + /* Enable the trace unit */ > + writel_relaxed(1, drvdata->base + TRCPRGCTLR); > + > + /* wait for TRCSTATR.IDLE to go back down to '0' */ > + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) > + dev_err(drvdata->dev, > + "timeout observed when probing at offset %#x\n", > + TRCSTATR); > + > + CS_LOCK(drvdata->base); > + > + dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); > +} > + > +static int etm4_enable(struct coresight_device *csdev) > +{ > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + int ret; > + > + pm_runtime_get_sync(drvdata->dev); > + spin_lock(&drvdata->spinlock); > + > + /* > + * Executing etm4_enable_hw on the cpu whose ETM is being enabled > + * ensures that register writes occur when cpu is powered. > + */ > + ret = smp_call_function_single(drvdata->cpu, > + etm4_enable_hw, drvdata, 1); > + if (ret) > + goto err; > + drvdata->enable = true; > + drvdata->sticky_enable = true; > + > + spin_unlock(&drvdata->spinlock); > + > + dev_info(drvdata->dev, "ETM tracing enabled\n"); > + return 0; > +err: > + spin_unlock(&drvdata->spinlock); > + pm_runtime_put(drvdata->dev); > + return ret; > +} > + > +static void etm4_disable_hw(void *info) > +{ > + u32 control; > + struct etmv4_drvdata *drvdata = info; > + > + CS_UNLOCK(drvdata->base); > + > + control = readl_relaxed(drvdata->base + TRCPRGCTLR); > + > + /* EN, bit[0] Trace unit enable bit */ > + control &= ~0x1; > + > + /* make sure everything completes before disabling */ > + mb(); > + isb(); > + writel_relaxed(control, drvdata->base + TRCPRGCTLR); > + > + CS_LOCK(drvdata->base); > + > + dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); > +} > + > +static void etm4_disable(struct coresight_device *csdev) > +{ > + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + /* > + * Taking hotplug lock here protects from clocks getting disabled > + * with tracing being left on (crash scenario) if user disable occurs > + * after cpu online mask indicates the cpu is offline but before the > + * DYING hotplug callback is serviced by the ETM driver. > + */ > + get_online_cpus(); > + spin_lock(&drvdata->spinlock); > + > + /* > + * Executing etm4_disable_hw on the cpu whose ETM is being disabled > + * ensures that register writes occur when cpu is powered. > + */ > + smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); > + drvdata->enable = false; > + > + spin_unlock(&drvdata->spinlock); > + put_online_cpus(); > + > + pm_runtime_put(drvdata->dev); > + > + dev_info(drvdata->dev, "ETM tracing disabled\n"); > +} > + > +static const struct coresight_ops_source etm4_source_ops = { > + .trace_id = etm4_trace_id, > + .enable = etm4_enable, > + .disable = etm4_disable, > +}; > + > +static const struct coresight_ops etm4_cs_ops = { > + .source_ops = &etm4_source_ops, > +}; > + > +static ssize_t status_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + int ret; > + unsigned long flags; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + pm_runtime_get_sync(drvdata->dev); > + > + spin_lock_irqsave(&drvdata->spinlock, flags); > + CS_UNLOCK(drvdata->base); > + ret = sprintf(buf, > + "TRCCONFIGR:\t0x%08x\n" > + "TRCEVENTCTL0R:\t0x%08x\n" > + "TRCEVENTCTL1R:\t0x%08x\n" > + "TRCSTALLCTLR:\t0x%08x\n" > + "TRCSYNCPR:\t0x%08x\n" > + "TRCTRACEIDR:\t0x%08x\n" > + "TRCTSCTLR:\t0x%08x\n" > + "TRCVDARCCTLR:\t0x%08x\n" > + "TRCVDCTLR:\t0x%08x\n" > + "TRCVDSACCTLR:\t0x%08x\n" > + "TRCVICTLR:\t0x%08x\n" > + "TRCVIIECTLR:\t0x%08x\n" > + "TRCVISSCTLR:\t0x%08x\n" > + "TRCPRGCTLR:\t0x%08x\n" > + "CPU affinity:\t%d\n", That is not one-value-per-file, as is the rules for sysfs. Sorry, please fix up. ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 02/11] coresight-etm4x: Controls pertaining to tracer configuration [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2015-05-06 15:27 ` [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 08/11] coresight-etm4x: Controls pertaining to the counter functions Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 11/11] coresight-etm4x: Controls pertaining to the VM ID functions Mathieu Poirier 3 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-api-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kaixu.xia-QSEj5FYQhm4dnm+yROfE0A, zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A, mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A From: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Tracers can be configured with various options at synthesis time and knowing what resources are available is important for SW configuration purposes. As such adding RO sysfs entries for characteristics related to the tracer implementation. Signed-off-by: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 61 +++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 117 +++++++++++++++++++++ 2 files changed, 178 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index a4b623871ca0..0f579eb24631 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -26,3 +26,64 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Description: (R) Provides value of all the ID registers (TRCIDRx). + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of PE comparator inputs that are + available for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of address comparator pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of counters that are available for + tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates how many external inputs are implemented. + +What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of Context ID comparators that are + available for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of VMID comparators that are available + for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of sequencer states that are implemented. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of resource selection pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (R) Indicates the number of single-shot comparator controls that + are available for tracing. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index db0bea4d4661..c7421f319350 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -268,6 +268,114 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static ssize_t nr_pe_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_pe_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_pe_cmp); + +static ssize_t nr_addr_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_addr_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_addr_cmp); + +static ssize_t nr_cntr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_cntr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_cntr); + +static ssize_t nr_ext_inp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ext_inp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ext_inp); + +static ssize_t numcidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numcidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numcidc); + +static ssize_t numvmidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numvmidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numvmidc); + +static ssize_t nrseqstate_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nrseqstate; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nrseqstate); + +static ssize_t nr_resource_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_resource; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_resource); + +static ssize_t nr_ss_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ss_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ss_cmp); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -412,6 +520,15 @@ static ssize_t trcidr_show(struct device *dev, static DEVICE_ATTR_RO(trcidr); static struct attribute *coresight_etmv4_attrs[] = { + &dev_attr_nr_pe_cmp.attr, + &dev_attr_nr_addr_cmp.attr, + &dev_attr_nr_cntr.attr, + &dev_attr_nr_ext_inp.attr, + &dev_attr_numcidc.attr, + &dev_attr_numvmidc.attr, + &dev_attr_nrseqstate.attr, + &dev_attr_nr_resource.attr, + &dev_attr_nr_ss_cmp.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 08/11] coresight-etm4x: Controls pertaining to the counter functions [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2015-05-06 15:27 ` [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 02/11] coresight-etm4x: Controls pertaining to tracer configuration Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 11/11] coresight-etm4x: Controls pertaining to the VM ID functions Mathieu Poirier 3 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-api-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kaixu.xia-QSEj5FYQhm4dnm+yROfE0A, zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A, mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A From: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Adding sysfs entries related to the counter functionality, more specifically to set, control and reload the counters. Signed-off-by: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 26 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 144 +++++++++++++++++++++ 2 files changed, 170 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 44723f2e107e..b4581c9426d3 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -216,3 +216,29 @@ KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. + +What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Select which counter unit to work with. + +What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) This sets or returns the reload count value of the + specific counter. + +What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) This sets or returns the current count value of the + specific counter. + +What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Controls the operation of the selected counter. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index ca89e7ba4b75..7d22a630ec8a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1567,6 +1567,146 @@ static ssize_t seq_reset_event_store(struct device *dev, } static DEVICE_ATTR_RW(seq_reset_event); +static ssize_t cntr_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->cntr_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_cntr) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->cntr_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_idx); + +static ssize_t cntrldvr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntrldvr[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntrldvr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > ETM_CNTR_MAX_VAL) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntrldvr[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntrldvr); + +static ssize_t cntr_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > ETM_CNTR_MAX_VAL) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntr_val[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_val); + +static ssize_t cntr_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntr_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntr_ctrl[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_ctrl); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1743,6 +1883,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, &dev_attr_seq_reset_event.attr, + &dev_attr_cntr_idx.attr, + &dev_attr_cntrldvr.attr, + &dev_attr_cntr_val.attr, + &dev_attr_cntr_ctrl.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 11/11] coresight-etm4x: Controls pertaining to the VM ID functions [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> ` (2 preceding siblings ...) 2015-05-06 15:27 ` [PATCH v3 08/11] coresight-etm4x: Controls pertaining to the counter functions Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 3 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-api-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kaixu.xia-QSEj5FYQhm4dnm+yROfE0A, zhang.chunyan-QSEj5FYQhm4dnm+yROfE0A, mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A From: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Adding sysfs entries to access and configure specifics about the virtual machine ID comparator functions. Signed-off-by: Pratik Patel <pratikp-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Signed-off-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 178 +++++++++++++++++++++ 2 files changed, 198 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 8b32cb7b9723..eb5153891919 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -273,3 +273,23 @@ KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). + +What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Select which virtual machine ID comparator to work with. + +What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Get/Set the virtual machine ID comparator value to + trigger on. + +What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +Description: (RW) Mask for all 8 virtual machine ID comparator value + registers (if implemented). diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index da1b3cdb0413..15bf5be5004a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1964,6 +1964,181 @@ static ssize_t ctxid_masks_store(struct device *dev, } static DEVICE_ATTR_RW(ctxid_masks); +static ssize_t vmid_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->vmid_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t vmid_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->numvmidc) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->vmid_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_idx); + +static ssize_t vmid_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = (unsigned long)drvdata->vmid_val[drvdata->vmid_idx]; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t vmid_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when vmid tracing is enabled, i.e. at least one + * vmid comparator is implemented and at least 8 bit vmid size + */ + if (!drvdata->vmid_size || !drvdata->numvmidc) + return -EINVAL; + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->vmid_val[drvdata->vmid_idx] = (u64)val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_val); + +static ssize_t vmid_masks_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + val1 = drvdata->vmid_mask0; + val2 = drvdata->vmid_mask1; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t vmid_masks_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 i, j, maskbyte; + unsigned long val1, val2, mask; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + /* + * only implemented when vmid tracing is enabled, i.e. at least one + * vmid comparator is implemented and at least 8 bit vmid size + */ + if (!drvdata->vmid_size || !drvdata->numvmidc) + return -EINVAL; + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + + /* + * each byte[0..3] controls mask value applied to vmid + * comparator[0..3] + */ + switch (drvdata->numvmidc) { + case 0x1: + /* COMP0, bits[7:0] */ + drvdata->vmid_mask0 = val1 & 0xFF; + break; + case 0x2: + /* COMP1, bits[15:8] */ + drvdata->vmid_mask0 = val1 & 0xFFFF; + break; + case 0x3: + /* COMP2, bits[23:16] */ + drvdata->vmid_mask0 = val1 & 0xFFFFFF; + break; + case 0x4: + /* COMP3, bits[31:24] */ + drvdata->vmid_mask0 = val1; + break; + case 0x5: + /* COMP4, bits[7:0] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFF; + break; + case 0x6: + /* COMP5, bits[15:8] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFFFF; + break; + case 0x7: + /* COMP6, bits[23:16] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFFFFFF; + break; + case 0x8: + /* COMP7, bits[31:24] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2; + break; + default: + break; + } + + /* + * If software sets a mask bit to 1, it must program relevant byte + * of vmid comparator value 0x0, otherwise behavior is unpredictable. + * For example, if bit[3] of vmid_mask0 is 1, we must clear bits[31:24] + * of vmid comparator0 value (corresponding to byte 0) register. + */ + mask = drvdata->vmid_mask0; + for (i = 0; i < drvdata->numvmidc; i++) { + /* mask value of corresponding vmid comparator */ + maskbyte = mask & ETMv4_EVENT_MASK; + /* + * each bit corresponds to a byte of respective vmid comparator + * value register + */ + for (j = 0; j < 8; j++) { + if (maskbyte & 1) + drvdata->vmid_val[i] &= ~(0xFF << (j * 8)); + maskbyte >>= 1; + } + /* Select the next vmid comparator mask value */ + if (i == 3) + /* vmid comparators[4-7] */ + mask = drvdata->vmid_mask1; + else + mask >>= 0x8; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_masks); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -2149,6 +2324,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_ctxid_idx.attr, &dev_attr_ctxid_val.attr, &dev_attr_ctxid_masks.attr, + &dev_attr_vmid_idx.attr, + &dev_attr_vmid_val.attr, + &dev_attr_vmid_masks.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 09/11] coresight-etm4x: Controls pertaining to the selection of resources 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier ` (5 preceding siblings ...) [not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> @ 2015-05-06 15:27 ` Mathieu Poirier 2015-05-06 15:27 ` [PATCH v3 10/11] coresight-etm4x: Controls pertaining to the context ID functions Mathieu Poirier 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan, mathieu.poirier From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to control the selection of the resources the trace unit will use as triggers to perform a trace run. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 12 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 75 ++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index b4581c9426d3..b5c0456290ab 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -242,3 +242,15 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the operation of the selected counter. + +What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Select which resource selection unit to work with. + +What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Controls the selection of the resources in the trace unit. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7d22a630ec8a..d578500f937d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1707,6 +1707,79 @@ static ssize_t cntr_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(cntr_ctrl); +static ssize_t res_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->res_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t res_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + /* Resource selector pair 0 is always implemented and reserved */ + if ((val == 0) || (val >= drvdata->nr_resource)) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->res_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(res_idx); + +static ssize_t res_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->res_idx; + val = drvdata->res_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t res_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->res_idx; + /* For odd idx pair inversal bit is RES0 */ + if (idx % 2 != 0) + /* PAIRINV, bit[21] */ + val &= ~BIT(21); + drvdata->res_ctrl[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(res_ctrl); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1887,6 +1960,8 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cntrldvr.attr, &dev_attr_cntr_val.attr, &dev_attr_cntr_ctrl.attr, + &dev_attr_res_idx.attr, + &dev_attr_res_ctrl.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 10/11] coresight-etm4x: Controls pertaining to the context ID functions 2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier ` (6 preceding siblings ...) 2015-05-06 15:27 ` [PATCH v3 09/11] coresight-etm4x: Controls pertaining to the selection of resources Mathieu Poirier @ 2015-05-06 15:27 ` Mathieu Poirier 7 siblings, 0 replies; 15+ messages in thread From: Mathieu Poirier @ 2015-05-06 15:27 UTC (permalink / raw) To: gregkh Cc: linux-arm-kernel, linux-api, linux-kernel, kaixu.xia, zhang.chunyan, mathieu.poirier From: Pratik Patel <pratikp@codeaurora.org> Adding sysfs entries to access and configure specifics about the context ID comparator functions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 19 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 187 +++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index b5c0456290ab..8b32cb7b9723 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -254,3 +254,22 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the selection of the resources in the trace unit. + +What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Select which context ID comparator to work with. + +What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Get/Set the context ID comparator value to trigger on. + +What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Mask for all 8 context ID comparator value + registers (if implemented). diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d578500f937d..da1b3cdb0413 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1780,6 +1780,190 @@ static ssize_t res_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(res_ctrl); +static ssize_t ctxid_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ctxid_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ctxid_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->numcidc) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->ctxid_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_idx); + +static ssize_t ctxid_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->ctxid_idx; + val = (unsigned long)drvdata->ctxid_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ctxid_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when ctxid tracing is enabled, i.e. at least one + * ctxid comparator is implemented and ctxid is greater than 0 bits + * in length + */ + if (!drvdata->ctxid_size || !drvdata->numcidc) + return -EINVAL; + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->ctxid_idx; + drvdata->ctxid_val[idx] = (u64)val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_val); + +static ssize_t ctxid_masks_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + val1 = drvdata->ctxid_mask0; + val2 = drvdata->ctxid_mask1; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t ctxid_masks_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 i, j, maskbyte; + unsigned long val1, val2, mask; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when ctxid tracing is enabled, i.e. at least one + * ctxid comparator is implemented and ctxid is greater than 0 bits + * in length + */ + if (!drvdata->ctxid_size || !drvdata->numcidc) + return -EINVAL; + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * each byte[0..3] controls mask value applied to ctxid + * comparator[0..3] + */ + switch (drvdata->numcidc) { + case 0x1: + /* COMP0, bits[7:0] */ + drvdata->ctxid_mask0 = val1 & 0xFF; + break; + case 0x2: + /* COMP1, bits[15:8] */ + drvdata->ctxid_mask0 = val1 & 0xFFFF; + break; + case 0x3: + /* COMP2, bits[23:16] */ + drvdata->ctxid_mask0 = val1 & 0xFFFFFF; + break; + case 0x4: + /* COMP3, bits[31:24] */ + drvdata->ctxid_mask0 = val1; + break; + case 0x5: + /* COMP4, bits[7:0] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFF; + break; + case 0x6: + /* COMP5, bits[15:8] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFFFF; + break; + case 0x7: + /* COMP6, bits[23:16] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFFFFFF; + break; + case 0x8: + /* COMP7, bits[31:24] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2; + break; + default: + break; + } + /* + * If software sets a mask bit to 1, it must program relevant byte + * of ctxid comparator value 0x0, otherwise behavior is unpredictable. + * For example, if bit[3] of ctxid_mask0 is 1, we must clear bits[31:24] + * of ctxid comparator0 value (corresponding to byte 0) register. + */ + mask = drvdata->ctxid_mask0; + for (i = 0; i < drvdata->numcidc; i++) { + /* mask value of corresponding ctxid comparator */ + maskbyte = mask & ETMv4_EVENT_MASK; + /* + * each bit corresponds to a byte of respective ctxid comparator + * value register + */ + for (j = 0; j < 8; j++) { + if (maskbyte & 1) + drvdata->ctxid_val[i] &= ~(0xFF << (j * 8)); + maskbyte >>= 1; + } + /* Select the next ctxid comparator mask value */ + if (i == 3) + /* ctxid comparators[4-7] */ + mask = drvdata->ctxid_mask1; + else + mask >>= 0x8; + } + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_masks); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1962,6 +2146,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cntr_ctrl.attr, &dev_attr_res_idx.attr, &dev_attr_res_ctrl.attr, + &dev_attr_ctxid_idx.attr, + &dev_attr_ctxid_val.attr, + &dev_attr_ctxid_masks.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr, -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-05-10 13:37 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
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2015-05-06 15:27 [PATCH v3 00/11] Support for coresight ETMv4 tracer Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 03/11] coresight-etm4x: Controls pertaining to the reset, mode, pe and events Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 04/11] coresight-etm4x: Controls pertaining to various configuration options Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 05/11] coresight-etm4x: Controls pertaining to the ViewInst register Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 06/11] coresight-etm4x: Controls pertaining to the address comparator functions Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 07/11] coresight-etm4x: Controls pertaining to the sequencer functions Mathieu Poirier
[not found] ` <1430926047-9125-1-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-05-06 15:27 ` [PATCH v3 01/11] coresight-etm4x: Adding CoreSight ETM4x driver Mathieu Poirier
[not found] ` <1430926047-9125-2-git-send-email-mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-05-08 8:27 ` Ivan T. Ivanov
2015-05-08 13:12 ` Mathieu Poirier
2015-05-10 13:37 ` Greg KH
2015-05-06 15:27 ` [PATCH v3 02/11] coresight-etm4x: Controls pertaining to tracer configuration Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 08/11] coresight-etm4x: Controls pertaining to the counter functions Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 11/11] coresight-etm4x: Controls pertaining to the VM ID functions Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 09/11] coresight-etm4x: Controls pertaining to the selection of resources Mathieu Poirier
2015-05-06 15:27 ` [PATCH v3 10/11] coresight-etm4x: Controls pertaining to the context ID functions Mathieu Poirier
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