[PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave Martin]

This series implements Linux kernel support for the ARM Scalable Vector
Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
and full cover letter.

This is a minor update to v4, but does contain a couple of important
fixes.

As in previous postings, the last two patches (here 29-30) are still
RFC and not proposed for merging at this time.

The patches apply on
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
for-next/core
d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")

To reduce spam, some people may not been copied on the entire series.
For those who did not receive the whole series, it can be found in the
linux-arm-kernel archive. [2]

See the individual patches for details of changes.

For reviewer convenience, a git tree is available. [4]

Since there are some changes against already-reviewed patches, I've also
pushed an unsquashed fixes tree for people to take a look at if it
helps. [5]


Summary:

 * "regset: Add support for dynamically sized regsets" fixed to avoid
   x86 breakage;

 * one trival arm64 patch added to add asmlinkage annotations, and a
   corresponding minor change to the Core task context handling patch;

 * one new arm64 fix ("signal: Verify extra data is user-readable in
   sys_rt_sigreturn") to ensure that access_ok() checks are done for the
   whole extended signal frame, not just the base frame;

 * one minor fix to the SVE sigreturn code to return consistent
   intermediate error values (semantic correctness, non-functional
   change);

 * one minor change to call __copy_from_user() instead of
   copy_from_user() in a situation where there is already an access_ok()
   check;


[1] ARM Scalable Vector Extension
https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture

[2] linux-arm-kernel October 2017 Archives by thread
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html

[3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html

[4] For review and testing only -- **do not pull**
    (This branch has review changelogs which should not form part of
    the final commits.)

    v5 series (this posting)

    http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
    git://linux-arm.org/linux-dm.git sve/v5

[5] For review and testing only -- **do not pull**
    (This branch has review changelogs which should not form part of
    the final commits.)

    v4 with unsquashed fixes

    http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
    git://linux-arm.org/linux-dm.git sve/v4+fixes


Dave Martin (30):
  regset: Add support for dynamically sized regsets
  arm64: fpsimd: Correctly annotate exception helpers called from asm
  arm64: signal: Verify extra data is user-readable in sys_rt_sigreturn
  arm64: KVM: Hide unsupported AArch64 CPU features from guests
  arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON
  arm64: Port deprecated instruction emulation to new sysctl interface
  arm64: fpsimd: Simplify uses of {set,clear}_ti_thread_flag()
  arm64/sve: System register and exception syndrome definitions
  arm64/sve: Low-level SVE architectural state manipulation functions
  arm64/sve: Kconfig update and conditional compilation support
  arm64/sve: Signal frame and context structure definition
  arm64/sve: Low-level CPU setup
  arm64/sve: Core task context handling
  arm64/sve: Support vector length resetting for new processes
  arm64/sve: Signal handling support
  arm64/sve: Backend logic for setting the vector length
  arm64: cpufeature: Move sys_caps_initialised declarations
  arm64/sve: Probe SVE capabilities and usable vector lengths
  arm64/sve: Preserve SVE registers around kernel-mode NEON use
  arm64/sve: Preserve SVE registers around EFI runtime service calls
  arm64/sve: ptrace and ELF coredump support
  arm64/sve: Add prctl controls for userspace vector length management
  arm64/sve: Add sysctl to set the default vector length for new
    processes
  arm64/sve: KVM: Prevent guests from using SVE
  arm64/sve: KVM: Treat guest SVE use as undefined instruction execution
  arm64/sve: KVM: Hide SVE from CPU features exposed to guests
  arm64/sve: Detect SVE and activate runtime support
  arm64/sve: Add documentation
  arm64: signal: Report signal frame size to userspace via auxv
  arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ

 Documentation/arm64/cpu-feature-registers.txt |   6 +-
 Documentation/arm64/elf_hwcaps.txt            |   4 +
 Documentation/arm64/sve.txt                   | 508 +++++++++++++++
 arch/arm/include/asm/kvm_host.h               |   3 +
 arch/arm64/Kconfig                            |  12 +
 arch/arm64/include/asm/cpu.h                  |   4 +
 arch/arm64/include/asm/cpucaps.h              |   3 +-
 arch/arm64/include/asm/cpufeature.h           |  42 ++
 arch/arm64/include/asm/elf.h                  |   5 +
 arch/arm64/include/asm/esr.h                  |   3 +-
 arch/arm64/include/asm/fpsimd.h               |  71 +-
 arch/arm64/include/asm/fpsimdmacros.h         | 148 +++++
 arch/arm64/include/asm/kvm_arm.h              |   5 +-
 arch/arm64/include/asm/kvm_host.h             |  11 +
 arch/arm64/include/asm/processor.h            |  10 +
 arch/arm64/include/asm/sysreg.h               |  24 +
 arch/arm64/include/asm/thread_info.h          |   5 +
 arch/arm64/include/asm/traps.h                |   2 +
 arch/arm64/include/uapi/asm/auxvec.h          |   3 +-
 arch/arm64/include/uapi/asm/hwcap.h           |   1 +
 arch/arm64/include/uapi/asm/ptrace.h          | 138 ++++
 arch/arm64/include/uapi/asm/sigcontext.h      | 120 +++-
 arch/arm64/kernel/armv8_deprecated.c          |  15 +-
 arch/arm64/kernel/cpufeature.c                |  99 ++-
 arch/arm64/kernel/cpuinfo.c                   |   7 +
 arch/arm64/kernel/entry-fpsimd.S              |  17 +
 arch/arm64/kernel/entry.S                     |  40 +-
 arch/arm64/kernel/fpsimd.c                    | 907 +++++++++++++++++++++++++-
 arch/arm64/kernel/head.S                      |  13 +-
 arch/arm64/kernel/process.c                   |  24 +
 arch/arm64/kernel/ptrace.c                    | 280 +++++++-
 arch/arm64/kernel/signal.c                    | 220 ++++++-
 arch/arm64/kernel/signal32.c                  |   2 +-
 arch/arm64/kernel/traps.c                     |   7 +-
 arch/arm64/kvm/handle_exit.c                  |   8 +
 arch/arm64/kvm/hyp/switch.c                   |  12 +-
 arch/arm64/kvm/sys_regs.c                     | 292 +++++++--
 fs/binfmt_elf.c                               |  10 +-
 include/linux/regset.h                        |  67 +-
 include/uapi/linux/elf.h                      |   1 +
 include/uapi/linux/prctl.h                    |   9 +
 kernel/sys.c                                  |  12 +
 virt/kvm/arm/arm.c                            |   3 +
 43 files changed, 3023 insertions(+), 150 deletions(-)
 create mode 100644 Documentation/arm64/sve.txt

-- 
2.1.4

[PATCH v5 28/30] arm64/sve: Add documentation

[Dave Martin]

This patch adds basic documentation of the user/kernel interface
provided by the for SVE.

Signed-off-by: Dave Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org>
Reviewed-by: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
Cc: Alan Hayward <alan.hayward-5wv7dgnIgG8@public.gmane.org>
Cc: Alex Bennée <alex.bennee-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Michael Kerrisk <mtk.manpages-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Szabolcs Nagy <szabolcs.nagy-5wv7dgnIgG8@public.gmane.org>
Cc: linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/arm64/sve.txt              | 508 +++++++++++++++++++++++++++++++
 arch/arm64/include/uapi/asm/sigcontext.h |   3 +
 2 files changed, 511 insertions(+)
 create mode 100644 Documentation/arm64/sve.txt

diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt
new file mode 100644
index 0000000..f128f73
--- /dev/null
+++ b/Documentation/arm64/sve.txt
@@ -0,0 +1,508 @@
+            Scalable Vector Extension support for AArch64 Linux
+            ===================================================
+
+Author: Dave Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org>
+Date:   4 August 2017
+
+This document outlines briefly the interface provided to userspace by Linux in
+order to support use of the ARM Scalable Vector Extension (SVE).
+
+This is an outline of the most important features and issues only and not
+intended to be exhaustive.
+
+This document does not aim to describe the SVE architecture or programmer's
+model.  To aid understanding, a minimal description of relevant programmer's
+model features for SVE is included in Appendix A.
+
+
+1.  General
+-----------
+
+* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
+  tracked per-thread.
+
+* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
+  AT_HWCAP entry.  Presence of this flag implies the presence of the SVE
+  instructions and registers, and the Linux-specific system interfaces
+  described in this document.  SVE is reported in /proc/cpuinfo as "sve".
+
+* Support for the execution of SVE instructions in userspace can also be
+  detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
+  instruction, and checking that the value of the SVE field is nonzero. [3]
+
+  It does not guarantee the presence of the system interfaces described in the
+  following sections: software that needs to verify that those interfaces are
+  present must check for HWCAP_SVE instead.
+
+* Debuggers should restrict themselves to interacting with the target via the
+  NT_ARM_SVE regset.  The recommended way of detecting support for this regset
+  is to connect to a target process first and then attempt a
+  ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
+
+
+2.  Vector length terminology
+-----------------------------
+
+The size of an SVE vector (Z) register is referred to as the "vector length".
+
+To avoid confusion about the units used to express vector length, the kernel
+adopts the following conventions:
+
+* Vector length (VL) = size of a Z-register in bytes
+
+* Vector quadwords (VQ) = size of a Z-register in units of 128 bits
+
+(So, VL = 16 * VQ.)
+
+The VQ convention is used where the underlying granularity is important, such
+as in data structure definitions.  In most other situations, the VL convention
+is used.  This is consistent with the meaning of the "VL" pseudo-register in
+the SVE instruction set architecture.
+
+
+3.  System call behaviour
+-------------------------
+
+* On syscall, V0..V31 are preserved (as without SVE).  Thus, bits [127:0] of
+  Z0..Z31 are preserved.  All other bits of Z0..Z31, and all of P0..P15 and FFR
+  become unspecified on return from a syscall.
+
+* The SVE registers are not used to pass arguments to or receive results from
+  any syscall.
+
+* In practice the affected registers/bits will be preserved or will be replaced
+  with zeros on return from a syscall, but userspace should not make
+  assumptions about this.  The kernel behaviour may vary on a case-by-case
+  basis.
+
+* All other SVE state of a thread, including the currently configured vector
+  length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
+  length (if any), is preserved across all syscalls, subject to the specific
+  exceptions for execve() described in section 6.
+
+  In particular, on return from a fork() or clone(), the parent and new child
+  process or thread share identical SVE configuration, matching that of the
+  parent before the call.
+
+
+4.  Signal handling
+-------------------
+
+* A new signal frame record sve_context encodes the SVE registers on signal
+  delivery. [1]
+
+* This record is supplementary to fpsimd_context.  The FPSR and FPCR registers
+  are only present in fpsimd_context.  For convenience, the content of V0..V31
+  is duplicated between sve_context and fpsimd_context.
+
+* The signal frame record for SVE always contains basic metadata, in particular
+  the thread's vector length (in sve_context.vl).
+
+* The SVE registers may or may not be included in the record, depending on
+  whether the registers are live for the thread.  The registers are present if
+  and only if:
+  sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
+
+* If the registers are present, the remainder of the record has a vl-dependent
+  size and layout.  Macros SVE_SIG_* are defined [1] to facilitate access to
+  the members.
+
+* If the SVE context is too big to fit in sigcontext.__reserved[], then extra
+  space is allocated on the stack, an extra_context record is written in
+  __reserved[] referencing this space.  sve_context is then written in the
+  extra space.  Refer to [1] for further details about this mechanism.
+
+
+5.  Signal return
+-----------------
+
+When returning from a signal handler:
+
+* If there is no sve_context record in the signal frame, or if the record is
+  present but contains no register data as desribed in the previous section,
+  then the SVE registers/bits become non-live and take unspecified values.
+
+* If sve_context is present in the signal frame and contains full register
+  data, the SVE registers become live and are populated with the specified
+  data.  However, for backward compatibility reasons, bits [127:0] of Z0..Z31
+  are always restored from the corresponding members of fpsimd_context.vregs[]
+  and not from sve_context.  The remaining bits are restored from sve_context.
+
+* Inclusion of fpsimd_context in the signal frame remains mandatory,
+  irrespective of whether sve_context is present or not.
+
+* The vector length cannot be changed via signal return.  If sve_context.vl in
+  the signal frame does not match the current vector length, the signal return
+  attempt is treated as illegal, resulting in a forced SIGSEGV.
+
+
+6.  prctl extensions
+--------------------
+
+Some new prctl() calls are added to allow programs to manage the SVE vector
+length:
+
+prctl(PR_SVE_SET_VL, unsigned long arg)
+
+    Sets the vector length of the calling thread and related flags, where
+    arg == vl | flags.  Other threads of the calling process are unaffected.
+
+    vl is the desired vector length, where sve_vl_valid(vl) must be true.
+
+    flags:
+
+	PR_SVE_SET_VL_INHERIT
+
+	    Inherit the current vector length across execve().  Otherwise, the
+	    vector length is reset to the system default at execve().  (See
+	    Section 9.)
+
+	PR_SVE_SET_VL_ONEXEC
+
+	    Defer the requested vector length change until the next execve()
+	    performed by this thread.
+
+	    The effect is equivalent to implicit exceution of the following
+	    call immediately after the next execve() (if any) by the thread:
+
+		prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
+
+	    This allows launching of a new program with a different vector
+	    length, while avoiding runtime side effects in the caller.
+
+
+	    Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
+	    immediately.
+
+
+    Return value: a nonnegative on success, or a negative value on error:
+	EINVAL: SVE not supported, invalid vector length requested, or
+	    invalid flags.
+
+
+    On success:
+
+    * Either the calling thread's vector length or the deferred vector length
+      to be applied at the next execve() by the thread (dependent on whether
+      PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
+      supported by the system that is less than or equal to vl.  If vl ==
+      SVE_VL_MAX, the value set will be the largest value supported by the
+      system.
+
+    * Any previously outstanding deferred vector length change in the calling
+      thread is cancelled.
+
+    * The returned value describes the resulting configuration, encoded as for
+      PR_SVE_GET_VL.  The vector length reported in this value is the new
+      current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
+      present in arg; otherwise, the reported vector length is the deferred
+      vector length that will be applied at the next execve() by the calling
+      thread.
+
+    * Changing the vector length causes all of P0..P15, FFR and all bits of
+      Z0..V31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
+      unspecified.  Calling PR_SVE_SET_VL with vl equal to the thread's current
+      vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
+      flag, does not constitute a change to the vector length for this purpose.
+
+
+prctl(PR_SVE_GET_VL)
+
+    Gets the vector length of the calling thread.
+
+    The following flag may be OR-ed into the result:
+
+	PR_SVE_SET_VL_INHERIT
+
+	    Vector length will be inherited across execve().
+
+    There is no way to determine whether there is an outstanding deferred
+    vector length change (which would only normally be the case between a
+    fork() or vfork() and the corresponding execve() in typical use).
+
+    To extract the vector length from the result, and it with
+    PR_SVE_VL_LEN_MASK.
+
+    Return value: a nonnegative value on success, or a negative value on error:
+	EINVAL: SVE not supported.
+
+
+7.  ptrace extensions
+---------------------
+
+* A new regset NT_ARM_SVE is defined for use with PTRACE_GETREGSET and
+  PTRACE_SETREGSET.
+
+  Refer to [2] for definitions.
+
+The regset data starts with struct user_sve_header, containing:
+
+    size
+
+	Size of the complete regset, in bytes.
+	This depends on vl and possibly on other things in the future.
+
+	If a call to PTRACE_GETREGSET requests less data than the value of
+	size, the caller can allocate a larger buffer and retry in order to
+	read the complete regset.
+
+    max_size
+
+	Maximum size in bytes that the regset can grow to for the target
+	thread.  The regset won't grow bigger than this even if the target
+	thread changes its vector length etc.
+
+    vl
+
+	Target thread's current vector length, in bytes.
+
+    max_vl
+
+	Maximum possible vector length for the target thread.
+
+    flags
+
+	either
+
+	    SVE_PT_REGS_FPSIMD
+
+		SVE registers are not live (GETREGSET) or are to be made
+		non-live (SETREGSET).
+
+		The payload is of type struct user_fpsimd_state, with the same
+		meaning as for NT_PRFPREG, starting at offset
+		SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.
+
+		Extra data might be appended in the future: the size of the
+		payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).
+
+		vq should be obtained using sve_vq_from_vl(vl).
+
+		or
+
+	    SVE_PT_REGS_SVE
+
+		SVE registers are live (GETREGSET) or are to be made live
+		(SETREGSET).
+
+		The payload contains the SVE register data, starting at offset
+		SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
+		size SVE_PT_SVE_SIZE(vq, flags);
+
+	... OR-ed with zero or more of the following flags, which have the same
+	meaning and behaviour as the corresponding PR_SET_VL_* flags:
+
+	    SVE_PT_VL_INHERIT
+
+	    SVE_PT_VL_ONEXEC (SETREGSET only).
+
+* The effects of changing the vector length and/or flags are equivalent to
+  those documented for PR_SVE_SET_VL.
+
+  The caller must make a further GETREGSET call if it needs to know what VL is
+  actually set by SETREGSET, unless is it known in advance that the requested
+  VL is supported.
+
+* In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
+  the header fields.  The SVE_PT_SVE_*() macros are provided to facilitate
+  access to the members.
+
+* In either case, for SETREGSET it is permissible to omit the payload, in which
+  case only the vector length and flags are changed (along with any
+  consequences of those changes).
+
+* For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
+  requested VL is not supported, the effect will be the same as if the
+  payload were omitted, except that an EIO error is reported.  No
+  attempt is made to translate the payload data to the correct layout
+  for the vector length actually set.  The thread's FPSIMD state is
+  preserved, but the remaining bits of the SVE registers become
+  unspecified.  It is up to the caller to translate the payload layout
+  for the actual VL and retry.
+
+* The effect of writing a partial, incomplete payload is unspecified.
+
+
+8.  ELF coredump extensions
+---------------------------
+
+* A NT_ARM_SVE note will be added to each coredump for each thread of the
+  dumped process.  The contents will be equivalent to the data that would have
+  been read if a PTRACE_GETREGSET of NT_ARM_SVE were executed for each thread
+  when the coredump was generated.
+
+
+9.  System runtime configuration
+--------------------------------
+
+* To mitigate the ABI impact of expansion of the signal frame, a policy
+  mechanism is provided for administrators, distro maintainers and developers
+  to set the default vector length for userspace processes:
+
+/proc/sys/abi/sve_default_vector_length
+
+    Writing the text representation of an integer to this file sets the system
+    default vector length to the specified value, unless the value is greater
+    than the maximum vector length supported by the system in which case the
+    default vector length is set to that maximum.
+
+    The result can be determined by reopening the file and reading its
+    contents.
+
+    At boot, the default vector length is initially set to 64 or the maximum
+    supported vector length, whichever is smaller.  This determines the initial
+    vector length of the init process (PID 1).
+
+    Reading this file returns the current system default vector length.
+
+* At every execve() call, the new vector length of the new process is set to
+  the system default vector length, unless
+
+    * PR_SVE_SET_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
+      calling thread, or
+
+    * a deferred vector length change is pending, established via the
+      PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
+
+* Modifying the system default vector length does not affect the vector length
+  of any existing process or thread that does not make an execve() call.
+
+
+Appendix A.  SVE programmer's model (informative)
+=================================================
+
+This section provides a minimal description of the additions made by SVE to the
+ARMv8-A programmer's model that are relevant to this document.
+
+Note: This section is for information only and not intended to be complete or
+to replace any architectural specification.
+
+A.1.  Registers
+---------------
+
+In A64 state, SVE adds the following:
+
+* 32 8VL-bit vector registers Z0..Z31
+  For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
+
+  A register write using a Vn register name zeros all bits of the corresponding
+  Zn except for bits [127:0].
+
+* 16 VL-bit predicate registers P0..P15
+
+* 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
+
+* a VL "pseudo-register" that determines the size of each vector register
+
+  The SVE instruction set architecture provides no way to write VL directly.
+  Instead, it can be modified only by EL1 and above, by writing appropriate
+  system registers.
+
+* The value of VL can be configured at runtime by EL1 and above:
+  16 <= VL <= VLmax, where VL must be a multiple of 16.
+
+* The maximum vector length is determined by the hardware:
+  16 <= VLmax <= 256.
+
+  (The SVE architecture specifies 256, but permits future architecture
+  revisions to raise this limit.)
+
+* FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
+  operations in a similar way to the way in which they interact with ARMv8
+  floating-point operations.
+
+         8VL-1                       128               0  bit index
+        +----          ////            -----------------+
+     Z0 |                               :       V0      |
+      :                                          :
+     Z7 |                               :       V7      |
+     Z8 |                               :     * V8      |
+      :                                       :  :
+    Z15 |                               :     *V15      |
+    Z16 |                               :      V16      |
+      :                                          :
+    Z31 |                               :      V31      |
+        +----          ////            -----------------+
+                                                 31    0
+         VL-1                  0                +-------+
+        +----       ////      --+          FPSR |       |
+     P0 |                       |               +-------+
+      : |                       |         *FPCR |       |
+    P15 |                       |               +-------+
+        +----       ////      --+
+    FFR |                       |               +-----+
+        +----       ////      --+            VL |     |
+                                                +-----+
+
+(*) callee-save:
+    This only applies to bits [63:0] of Z-/V-registers.
+    FPCR contains callee-save and caller-save bits.  See [4] for details.
+
+
+A.2.  Procedure call standard
+-----------------------------
+
+The ARMv8-A base procedure call standard is extended as follows with respect to
+the additional SVE register state:
+
+* All SVE register bits that are not shared with FP/SIMD are caller-save.
+
+* Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
+
+  This follows from the way these bits are mapped to V8..V15, which are caller-
+  save in the base procedure call standard.
+
+
+Appendix B.  ARMv8-A FP/SIMD programmer's model
+===============================================
+
+Note: This section is for information only and not intended to be complete or
+to replace any architectural specification.
+
+Refer to [4] for for more information.
+
+ARMv8-A defines the following floating-point / SIMD register state:
+
+* 32 128-bit vector registers V0..V31
+* 2 32-bit status/control registers FPSR, FPCR
+
+         127           0  bit index
+        +---------------+
+     V0 |               |
+      : :               :
+     V7 |               |
+   * V8 |               |
+   :  : :               :
+   *V15 |               |
+    V16 |               |
+      : :               :
+    V31 |               |
+        +---------------+
+
+                 31    0
+                +-------+
+           FPSR |       |
+                +-------+
+          *FPCR |       |
+                +-------+
+
+(*) callee-save:
+    This only applies to bits [63:0] of V-registers.
+    FPCR contains a mixture of callee-save and caller-save bits.
+
+
+References
+==========
+
+[1] arch/arm64/include/uapi/asm/sigcontext.h
+    AArch64 Linux signal ABI definitions
+
+[2] arch/arm64/include/uapi/asm/ptrace.h
+    AArch64 Linux ptrace ABI definitions
+
+[3] linux/Documentation/arm64/cpu-feature-registers.txt
+
+[4] ARM IHI0055C
+    http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
+    http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
+    Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h
index 7654a81..3c0b484 100644
--- a/arch/arm64/include/uapi/asm/sigcontext.h
+++ b/arch/arm64/include/uapi/asm/sigcontext.h
@@ -133,6 +133,9 @@ struct sve_context {
  * The SVE architecture leaves space for future expansion of the
  * vector length beyond its initial architectural limit of 2048 bits
  * (16 quadwords).
+ *
+ * See linux/Documentation/arm64/sve.txt for a description of the VL/VQ
+ * terminology.
  */
 #define SVE_VQ_BYTES		16	/* number of bytes per quadword */
 
-- 
2.1.4

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Will Deacon]

On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> This series implements Linux kernel support for the ARM Scalable Vector
> Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> and full cover letter.
> 
> This is a minor update to v4, but does contain a couple of important
> fixes.

I've pushed a version of this series out to the arm64 devel branch, with
a view to putting it into next.

git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git devel

Please kick the tyres and let me know of any issues ASAP.

Will

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave P Martin]

On Thu, Nov 02, 2017 at 04:32:49PM +0000, Will Deacon wrote:
> On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> > This series implements Linux kernel support for the ARM Scalable Vector
> > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > and full cover letter.
> >
> > This is a minor update to v4, but does contain a couple of important
> > fixes.
>
> I've pushed a version of this series out to the arm64 devel branch, with
> a view to putting it into next.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git devel
>
> Please kick the tyres and let me know of any issues ASAP.

No obvious problems so far.

Cheers
---Dave
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Alex Bennée]

Dave Martin <Dave.Martin@arm.com> writes:

> This series implements Linux kernel support for the ARM Scalable Vector
> Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> and full cover letter.
>
> This is a minor update to v4, but does contain a couple of important
> fixes.
<snip>

I seem to have run into a regression with normal non-SVE sigcontexts
while trying to run consecutive RISU runs in the Foundation Model. I'm
failing to get repeatable results playing back a previous --master run.
It works OK with the default Debian kernel.

What is the current status of the tree? I'd like to try an narrow it
down but I seem to recall it was now in a next tree somewhere?

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Will Deacon]

On Wed, Nov 29, 2017 at 03:04:12PM +0000, Alex Bennée wrote:
> 
> Dave Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org> writes:
> 
> > This series implements Linux kernel support for the ARM Scalable Vector
> > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > and full cover letter.
> >
> > This is a minor update to v4, but does contain a couple of important
> > fixes.
> <snip>
> 
> I seem to have run into a regression with normal non-SVE sigcontexts
> while trying to run consecutive RISU runs in the Foundation Model. I'm
> failing to get repeatable results playing back a previous --master run.
> It works OK with the default Debian kernel.
> 
> What is the current status of the tree? I'd like to try an narrow it
> down but I seem to recall it was now in a next tree somewhere?

This is in mainline now, so please give a 4.15-rc1 build a spin. If there's
a user-visible regression then we need to get to the bottom of it ASAP.

Will

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave Martin]

On Wed, Nov 29, 2017 at 03:21:40PM +0000, Will Deacon wrote:
> On Wed, Nov 29, 2017 at 03:04:12PM +0000, Alex Bennée wrote:
> > 
> > Dave Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org> writes:
> > 
> > > This series implements Linux kernel support for the ARM Scalable Vector
> > > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > > and full cover letter.
> > >
> > > This is a minor update to v4, but does contain a couple of important
> > > fixes.
> > <snip>
> > 
> > I seem to have run into a regression with normal non-SVE sigcontexts
> > while trying to run consecutive RISU runs in the Foundation Model. I'm
> > failing to get repeatable results playing back a previous --master run.
> > It works OK with the default Debian kernel.
> > 
> > What is the current status of the tree? I'd like to try an narrow it
> > down but I seem to recall it was now in a next tree somewhere?
> 
> This is in mainline now, so please give a 4.15-rc1 build a spin. If there's
> a user-visible regression then we need to get to the bottom of it ASAP.
> 
> Will

The other significant change was in v4.13, where the signal frame
parser rework landed.

What upstream version is your known-good Debian kernel based on?

Cheers
---Dave

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Yury Norov]

On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> This series implements Linux kernel support for the ARM Scalable Vector
> Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> and full cover letter.
> 
> This is a minor update to v4, but does contain a couple of important
> fixes.
> 
> As in previous postings, the last two patches (here 29-30) are still
> RFC and not proposed for merging at this time.
> 
> The patches apply on
> git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> for-next/core
> d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")
> 
> To reduce spam, some people may not been copied on the entire series.
> For those who did not receive the whole series, it can be found in the
> linux-arm-kernel archive. [2]
> 
> See the individual patches for details of changes.
> 
> For reviewer convenience, a git tree is available. [4]
> 
> Since there are some changes against already-reviewed patches, I've also
> pushed an unsquashed fixes tree for people to take a look at if it
> helps. [5]
> 
> 
> Summary:
> 
>  * "regset: Add support for dynamically sized regsets" fixed to avoid
>    x86 breakage;
> 
>  * one trival arm64 patch added to add asmlinkage annotations, and a
>    corresponding minor change to the Core task context handling patch;
> 
>  * one new arm64 fix ("signal: Verify extra data is user-readable in
>    sys_rt_sigreturn") to ensure that access_ok() checks are done for the
>    whole extended signal frame, not just the base frame;
> 
>  * one minor fix to the SVE sigreturn code to return consistent
>    intermediate error values (semantic correctness, non-functional
>    change);
> 
>  * one minor change to call __copy_from_user() instead of
>    copy_from_user() in a situation where there is already an access_ok()
>    check;
> 
> 
> [1] ARM Scalable Vector Extension
> https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
> 
> [2] linux-arm-kernel October 2017 Archives by thread
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html
> 
> [3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html
> 
> [4] For review and testing only -- **do not pull**
>     (This branch has review changelogs which should not form part of
>     the final commits.)
> 
>     v5 series (this posting)
> 
>     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
>     git://linux-arm.org/linux-dm.git sve/v5
> 
> [5] For review and testing only -- **do not pull**
>     (This branch has review changelogs which should not form part of
>     the final commits.)
> 
>     v4 with unsquashed fixes
> 
>     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
>     git://linux-arm.org/linux-dm.git sve/v4+fixes

Hi Dave,

During rebase of my ILP32 series on 4.15 kernel I found that 
ILP32 needs to be enabled with SVE support, like you do for 
LP64 in this series.

I did all rebase work on this draft branch:
https://github.com/norov/linux/tree/ilp32-4.15-rc7

But any ILP32 program I tried crash, and the message in dmesg looks
like this:
[   39.510667] CPU: 0 PID: 1857 Comm: mytime Not tainted 4.15.0-rc7-00028-g45e0659df4d9 #41
[   39.510712] Hardware name: linux,dummy-virt (DT)
[   39.510829] pstate: 00000000 (nzcv daif -PAN -UAO)
[   39.511101] pc : 0x33488e28
[   39.511125] lr : 0x33488e28
[   39.511138] sp : 00000000fffef670
[   39.511158] x29: 000000005a536c33 x28: 0000000000000000 
[   39.511211] x27: 0000000000000000 x26: 0000000000000000 
[   39.511235] x25: 0000000000000000 x24: 0000000000000000 
[   39.511257] x23: 0000000000466000 x22: 0000000000000000 
[   39.511278] x21: 0000000000000000 x20: 000000000047f2a8 
[   39.511300] x19: 0000000000000000 x18: 0000000000000001 
[   39.511321] x17: 0000000000001000 x16: 0000000000001030 
[   39.511342] x15: 0000000000554e47 x14: 0000000000000001 
[   39.511364] x13: 0000000000000004 x12: 000000000000003c 
[   39.511385] x11: 0000100000000000 x10: 0800000000000000 
[   39.511406] x9 : 0fffffffffffffff x8 : 000000000000007c 
[   39.511427] x7 : 0000000000000077 x6 : 0000000000000041 
[   39.511448] x5 : 0000000000000411 x4 : 00000000fbad2488 
[   39.511468] x3 : 0000000000000001 x2 : 0000000000497950 
[   39.511489] x1 : 0000000000497550 x0 : 0000000000000001

(PC, LR and other registers may differ depending on test)

I'm pretty sure that this is SVE-related issue because if I disable
ARM64_SVE in config, everything becomes working.

I didn't get deep enough into this yet, and most probably there's
some stupid reason for crashing apps on my side, but in mail list
I found some sve-related patches that I cannot apply both on 4.15-rc
and next-20180108. And according to patch names, it is important
fixes, like this one:
https://www.spinics.net/lists/arm-kernel/msg619548.html

ILP32 code may spit some kernel issues from time to time, so there's
minor chance that the problem is not in ILP32 itself - that's why I
write this email to you.

What I want to ask you, do you have some branch with the most recent
SVE code that includes all fixes? Better if it would be 4.15-based
series, because we don't support ILP32 on next-* kernels now.

Also, if you have few minutes to take look at my series, I would
kindly ask you do this, because I still think that this is my
misunderstanding of how SVE should work for ILP32, and you as author
may just catch the bug at a glance.

Thanks,
Yury

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Yury Norov]

On Mon, Jan 08, 2018 at 05:49:05PM +0300, Yury Norov wrote:
> On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> > This series implements Linux kernel support for the ARM Scalable Vector
> > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > and full cover letter.
> > 
> > This is a minor update to v4, but does contain a couple of important
> > fixes.
> > 
> > As in previous postings, the last two patches (here 29-30) are still
> > RFC and not proposed for merging at this time.
> > 
> > The patches apply on
> > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > for-next/core
> > d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")
> > 
> > To reduce spam, some people may not been copied on the entire series.
> > For those who did not receive the whole series, it can be found in the
> > linux-arm-kernel archive. [2]
> > 
> > See the individual patches for details of changes.
> > 
> > For reviewer convenience, a git tree is available. [4]
> > 
> > Since there are some changes against already-reviewed patches, I've also
> > pushed an unsquashed fixes tree for people to take a look at if it
> > helps. [5]
> > 
> > 
> > Summary:
> > 
> >  * "regset: Add support for dynamically sized regsets" fixed to avoid
> >    x86 breakage;
> > 
> >  * one trival arm64 patch added to add asmlinkage annotations, and a
> >    corresponding minor change to the Core task context handling patch;
> > 
> >  * one new arm64 fix ("signal: Verify extra data is user-readable in
> >    sys_rt_sigreturn") to ensure that access_ok() checks are done for the
> >    whole extended signal frame, not just the base frame;
> > 
> >  * one minor fix to the SVE sigreturn code to return consistent
> >    intermediate error values (semantic correctness, non-functional
> >    change);
> > 
> >  * one minor change to call __copy_from_user() instead of
> >    copy_from_user() in a situation where there is already an access_ok()
> >    check;
> > 
> > 
> > [1] ARM Scalable Vector Extension
> > https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
> > 
> > [2] linux-arm-kernel October 2017 Archives by thread
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html
> > 
> > [3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html
> > 
> > [4] For review and testing only -- **do not pull**
> >     (This branch has review changelogs which should not form part of
> >     the final commits.)
> > 
> >     v5 series (this posting)
> > 
> >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
> >     git://linux-arm.org/linux-dm.git sve/v5
> > 
> > [5] For review and testing only -- **do not pull**
> >     (This branch has review changelogs which should not form part of
> >     the final commits.)
> > 
> >     v4 with unsquashed fixes
> > 
> >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
> >     git://linux-arm.org/linux-dm.git sve/v4+fixes
> 
> Hi Dave,
> 
> During rebase of my ILP32 series on 4.15 kernel I found that 
> ILP32 needs to be enabled with SVE support, like you do for 
> LP64 in this series.
> 
> I did all rebase work on this draft branch:
> https://github.com/norov/linux/tree/ilp32-4.15-rc7
> 
> But any ILP32 program I tried crash, and the message in dmesg looks
> like this:
> [   39.510667] CPU: 0 PID: 1857 Comm: mytime Not tainted 4.15.0-rc7-00028-g45e0659df4d9 #41
> [   39.510712] Hardware name: linux,dummy-virt (DT)
> [   39.510829] pstate: 00000000 (nzcv daif -PAN -UAO)
> [   39.511101] pc : 0x33488e28
> [   39.511125] lr : 0x33488e28
> [   39.511138] sp : 00000000fffef670
> [   39.511158] x29: 000000005a536c33 x28: 0000000000000000 
> [   39.511211] x27: 0000000000000000 x26: 0000000000000000 
> [   39.511235] x25: 0000000000000000 x24: 0000000000000000 
> [   39.511257] x23: 0000000000466000 x22: 0000000000000000 
> [   39.511278] x21: 0000000000000000 x20: 000000000047f2a8 
> [   39.511300] x19: 0000000000000000 x18: 0000000000000001 
> [   39.511321] x17: 0000000000001000 x16: 0000000000001030 
> [   39.511342] x15: 0000000000554e47 x14: 0000000000000001 
> [   39.511364] x13: 0000000000000004 x12: 000000000000003c 
> [   39.511385] x11: 0000100000000000 x10: 0800000000000000 
> [   39.511406] x9 : 0fffffffffffffff x8 : 000000000000007c 
> [   39.511427] x7 : 0000000000000077 x6 : 0000000000000041 
> [   39.511448] x5 : 0000000000000411 x4 : 00000000fbad2488 
> [   39.511468] x3 : 0000000000000001 x2 : 0000000000497950 
> [   39.511489] x1 : 0000000000497550 x0 : 0000000000000001

Hi Dave,

I fixed the crash. It was my local problem.

Thanks,
Yury

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave Martin]

On Mon, Jan 08, 2018 at 05:49:05PM +0300, Yury Norov wrote:
> On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> > This series implements Linux kernel support for the ARM Scalable Vector
> > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > and full cover letter.
> > 
> > This is a minor update to v4, but does contain a couple of important
> > fixes.
> > 
> > As in previous postings, the last two patches (here 29-30) are still
> > RFC and not proposed for merging at this time.
> > 
> > The patches apply on
> > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > for-next/core
> > d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")
> > 
> > To reduce spam, some people may not been copied on the entire series.
> > For those who did not receive the whole series, it can be found in the
> > linux-arm-kernel archive. [2]
> > 
> > See the individual patches for details of changes.
> > 
> > For reviewer convenience, a git tree is available. [4]
> > 
> > Since there are some changes against already-reviewed patches, I've also
> > pushed an unsquashed fixes tree for people to take a look at if it
> > helps. [5]
> > 
> > 
> > Summary:
> > 
> >  * "regset: Add support for dynamically sized regsets" fixed to avoid
> >    x86 breakage;
> > 
> >  * one trival arm64 patch added to add asmlinkage annotations, and a
> >    corresponding minor change to the Core task context handling patch;
> > 
> >  * one new arm64 fix ("signal: Verify extra data is user-readable in
> >    sys_rt_sigreturn") to ensure that access_ok() checks are done for the
> >    whole extended signal frame, not just the base frame;
> > 
> >  * one minor fix to the SVE sigreturn code to return consistent
> >    intermediate error values (semantic correctness, non-functional
> >    change);
> > 
> >  * one minor change to call __copy_from_user() instead of
> >    copy_from_user() in a situation where there is already an access_ok()
> >    check;
> > 
> > 
> > [1] ARM Scalable Vector Extension
> > https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
> > 
> > [2] linux-arm-kernel October 2017 Archives by thread
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html
> > 
> > [3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html
> > 
> > [4] For review and testing only -- **do not pull**
> >     (This branch has review changelogs which should not form part of
> >     the final commits.)
> > 
> >     v5 series (this posting)
> > 
> >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
> >     git://linux-arm.org/linux-dm.git sve/v5
> > 
> > [5] For review and testing only -- **do not pull**
> >     (This branch has review changelogs which should not form part of
> >     the final commits.)
> > 
> >     v4 with unsquashed fixes
> > 
> >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
> >     git://linux-arm.org/linux-dm.git sve/v4+fixes
> 
> Hi Dave,
> 
> During rebase of my ILP32 series on 4.15 kernel I found that 
> ILP32 needs to be enabled with SVE support, like you do for 
> LP64 in this series.
> 
> I did all rebase work on this draft branch:
> https://github.com/norov/linux/tree/ilp32-4.15-rc7
> 
> But any ILP32 program I tried crash, and the message in dmesg looks
> like this:
> [   39.510667] CPU: 0 PID: 1857 Comm: mytime Not tainted 4.15.0-rc7-00028-g45e0659df4d9 #41
> [   39.510712] Hardware name: linux,dummy-virt (DT)
> [   39.510829] pstate: 00000000 (nzcv daif -PAN -UAO)
> [   39.511101] pc : 0x33488e28
> [   39.511125] lr : 0x33488e28
> [   39.511138] sp : 00000000fffef670
> [   39.511158] x29: 000000005a536c33 x28: 0000000000000000 
> [   39.511211] x27: 0000000000000000 x26: 0000000000000000 
> [   39.511235] x25: 0000000000000000 x24: 0000000000000000 
> [   39.511257] x23: 0000000000466000 x22: 0000000000000000 
> [   39.511278] x21: 0000000000000000 x20: 000000000047f2a8 
> [   39.511300] x19: 0000000000000000 x18: 0000000000000001 
> [   39.511321] x17: 0000000000001000 x16: 0000000000001030 
> [   39.511342] x15: 0000000000554e47 x14: 0000000000000001 
> [   39.511364] x13: 0000000000000004 x12: 000000000000003c 
> [   39.511385] x11: 0000100000000000 x10: 0800000000000000 
> [   39.511406] x9 : 0fffffffffffffff x8 : 000000000000007c 
> [   39.511427] x7 : 0000000000000077 x6 : 0000000000000041 
> [   39.511448] x5 : 0000000000000411 x4 : 00000000fbad2488 
> [   39.511468] x3 : 0000000000000001 x2 : 0000000000497950 
> [   39.511489] x1 : 0000000000497550 x0 : 0000000000000001
> 
> (PC, LR and other registers may differ depending on test)
> 
> I'm pretty sure that this is SVE-related issue because if I disable
> ARM64_SVE in config, everything becomes working.

Really, software that does not use SVE should not see any difference.

Do you see any pattern to the failures?  Do they appear to be signal-
related?

Are you running on the SVE-enabled model, or is this on hardware?

> I didn't get deep enough into this yet, and most probably there's
> some stupid reason for crashing apps on my side, but in mail list
> I found some sve-related patches that I cannot apply both on 4.15-rc
> and next-20180108. And according to patch names, it is important
> fixes, like this one:
> https://www.spinics.net/lists/arm-kernel/msg619548.html
> 
> ILP32 code may spit some kernel issues from time to time, so there's
> minor chance that the problem is not in ILP32 itself - that's why I
> write this email to you.
> 
> What I want to ask you, do you have some branch with the most recent
> SVE code that includes all fixes? Better if it would be 4.15-based
> series, because we don't support ILP32 on next-* kernels now.

The above fix was queued for -rc2.  All pending fixes should be in
mainline by now.

> Also, if you have few minutes to take look at my series, I would
> kindly ask you do this, because I still think that this is my
> misunderstanding of how SVE should work for ILP32, and you as author
> may just catch the bug at a glance.

I'll take a look -- I didn't think that carefully about the ILP32
case so far, because it "should" be straightforward.  But there may
be gotchas I hadn't considered so far.

Cheers
---Dave

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave Martin]

On Tue, Jan 09, 2018 at 07:51:20PM +0300, Yury Norov wrote:
> On Mon, Jan 08, 2018 at 05:49:05PM +0300, Yury Norov wrote:
> > On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> > > This series implements Linux kernel support for the ARM Scalable Vector
> > > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > > and full cover letter.
> > > 
> > > This is a minor update to v4, but does contain a couple of important
> > > fixes.
> > > 
> > > As in previous postings, the last two patches (here 29-30) are still
> > > RFC and not proposed for merging at this time.
> > > 
> > > The patches apply on
> > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > > for-next/core
> > > d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")
> > > 
> > > To reduce spam, some people may not been copied on the entire series.
> > > For those who did not receive the whole series, it can be found in the
> > > linux-arm-kernel archive. [2]
> > > 
> > > See the individual patches for details of changes.
> > > 
> > > For reviewer convenience, a git tree is available. [4]
> > > 
> > > Since there are some changes against already-reviewed patches, I've also
> > > pushed an unsquashed fixes tree for people to take a look at if it
> > > helps. [5]
> > > 
> > > 
> > > Summary:
> > > 
> > >  * "regset: Add support for dynamically sized regsets" fixed to avoid
> > >    x86 breakage;
> > > 
> > >  * one trival arm64 patch added to add asmlinkage annotations, and a
> > >    corresponding minor change to the Core task context handling patch;
> > > 
> > >  * one new arm64 fix ("signal: Verify extra data is user-readable in
> > >    sys_rt_sigreturn") to ensure that access_ok() checks are done for the
> > >    whole extended signal frame, not just the base frame;
> > > 
> > >  * one minor fix to the SVE sigreturn code to return consistent
> > >    intermediate error values (semantic correctness, non-functional
> > >    change);
> > > 
> > >  * one minor change to call __copy_from_user() instead of
> > >    copy_from_user() in a situation where there is already an access_ok()
> > >    check;
> > > 
> > > 
> > > [1] ARM Scalable Vector Extension
> > > https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
> > > 
> > > [2] linux-arm-kernel October 2017 Archives by thread
> > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html
> > > 
> > > [3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
> > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html
> > > 
> > > [4] For review and testing only -- **do not pull**
> > >     (This branch has review changelogs which should not form part of
> > >     the final commits.)
> > > 
> > >     v5 series (this posting)
> > > 
> > >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
> > >     git://linux-arm.org/linux-dm.git sve/v5
> > > 
> > > [5] For review and testing only -- **do not pull**
> > >     (This branch has review changelogs which should not form part of
> > >     the final commits.)
> > > 
> > >     v4 with unsquashed fixes
> > > 
> > >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
> > >     git://linux-arm.org/linux-dm.git sve/v4+fixes
> > 
> > Hi Dave,
> > 
> > During rebase of my ILP32 series on 4.15 kernel I found that 
> > ILP32 needs to be enabled with SVE support, like you do for 
> > LP64 in this series.
> > 
> > I did all rebase work on this draft branch:
> > https://github.com/norov/linux/tree/ilp32-4.15-rc7
> > 
> > But any ILP32 program I tried crash, and the message in dmesg looks
> > like this:
> > [   39.510667] CPU: 0 PID: 1857 Comm: mytime Not tainted 4.15.0-rc7-00028-g45e0659df4d9 #41
> > [   39.510712] Hardware name: linux,dummy-virt (DT)
> > [   39.510829] pstate: 00000000 (nzcv daif -PAN -UAO)
> > [   39.511101] pc : 0x33488e28
> > [   39.511125] lr : 0x33488e28
> > [   39.511138] sp : 00000000fffef670
> > [   39.511158] x29: 000000005a536c33 x28: 0000000000000000 
> > [   39.511211] x27: 0000000000000000 x26: 0000000000000000 
> > [   39.511235] x25: 0000000000000000 x24: 0000000000000000 
> > [   39.511257] x23: 0000000000466000 x22: 0000000000000000 
> > [   39.511278] x21: 0000000000000000 x20: 000000000047f2a8 
> > [   39.511300] x19: 0000000000000000 x18: 0000000000000001 
> > [   39.511321] x17: 0000000000001000 x16: 0000000000001030 
> > [   39.511342] x15: 0000000000554e47 x14: 0000000000000001 
> > [   39.511364] x13: 0000000000000004 x12: 000000000000003c 
> > [   39.511385] x11: 0000100000000000 x10: 0800000000000000 
> > [   39.511406] x9 : 0fffffffffffffff x8 : 000000000000007c 
> > [   39.511427] x7 : 0000000000000077 x6 : 0000000000000041 
> > [   39.511448] x5 : 0000000000000411 x4 : 00000000fbad2488 
> > [   39.511468] x3 : 0000000000000001 x2 : 0000000000497950 
> > [   39.511489] x1 : 0000000000497550 x0 : 0000000000000001
> 
> Hi Dave,
> 
> I fixed the crash. It was my local problem.

Ah, right :)

I'll take a look at your code anyway in case there's something
else one of us didn't think of.

Cheers
---Dave

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Yury Norov]

On Mon, Jan 15, 2018 at 05:22:01PM +0000, Dave Martin wrote:
> On Tue, Jan 09, 2018 at 07:51:20PM +0300, Yury Norov wrote:
> > On Mon, Jan 08, 2018 at 05:49:05PM +0300, Yury Norov wrote:
> > > On Tue, Oct 31, 2017 at 03:50:52PM +0000, Dave Martin wrote:
> > > > This series implements Linux kernel support for the ARM Scalable Vector
> > > > Extension (SVE). [1]  It supersedes the previous v3: see [3] for link
> > > > and full cover letter.
> > > > 
> > > > This is a minor update to v4, but does contain a couple of important
> > > > fixes.
> > > > 
> > > > As in previous postings, the last two patches (here 29-30) are still
> > > > RFC and not proposed for merging at this time.
> > > > 
> > > > The patches apply on
> > > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > > > for-next/core
> > > > d7b1d22d3821 ("arm64: uapi: Remove PSR_Q_BIT")
> > > > 
> > > > To reduce spam, some people may not been copied on the entire series.
> > > > For those who did not receive the whole series, it can be found in the
> > > > linux-arm-kernel archive. [2]
> > > > 
> > > > See the individual patches for details of changes.
> > > > 
> > > > For reviewer convenience, a git tree is available. [4]
> > > > 
> > > > Since there are some changes against already-reviewed patches, I've also
> > > > pushed an unsquashed fixes tree for people to take a look at if it
> > > > helps. [5]
> > > > 
> > > > 
> > > > Summary:
> > > > 
> > > >  * "regset: Add support for dynamically sized regsets" fixed to avoid
> > > >    x86 breakage;
> > > > 
> > > >  * one trival arm64 patch added to add asmlinkage annotations, and a
> > > >    corresponding minor change to the Core task context handling patch;
> > > > 
> > > >  * one new arm64 fix ("signal: Verify extra data is user-readable in
> > > >    sys_rt_sigreturn") to ensure that access_ok() checks are done for the
> > > >    whole extended signal frame, not just the base frame;
> > > > 
> > > >  * one minor fix to the SVE sigreturn code to return consistent
> > > >    intermediate error values (semantic correctness, non-functional
> > > >    change);
> > > > 
> > > >  * one minor change to call __copy_from_user() instead of
> > > >    copy_from_user() in a situation where there is already an access_ok()
> > > >    check;
> > > > 
> > > > 
> > > > [1] ARM Scalable Vector Extension
> > > > https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
> > > > 
> > > > [2] linux-arm-kernel October 2017 Archives by thread
> > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/thread.html
> > > > 
> > > > [3] [PATCH v4 00/28] ARM Scalable Vector Extension (SVE)
> > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-October/539414.html
> > > > 
> > > > [4] For review and testing only -- **do not pull**
> > > >     (This branch has review changelogs which should not form part of
> > > >     the final commits.)
> > > > 
> > > >     v5 series (this posting)
> > > > 
> > > >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v5
> > > >     git://linux-arm.org/linux-dm.git sve/v5
> > > > 
> > > > [5] For review and testing only -- **do not pull**
> > > >     (This branch has review changelogs which should not form part of
> > > >     the final commits.)
> > > > 
> > > >     v4 with unsquashed fixes
> > > > 
> > > >     http://linux-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve/v4%2Bfixes
> > > >     git://linux-arm.org/linux-dm.git sve/v4+fixes
> > > 
> > > Hi Dave,
> > > 
> > > During rebase of my ILP32 series on 4.15 kernel I found that 
> > > ILP32 needs to be enabled with SVE support, like you do for 
> > > LP64 in this series.
> > > 
> > > I did all rebase work on this draft branch:
> > > https://github.com/norov/linux/tree/ilp32-4.15-rc7
> > > 
> > > But any ILP32 program I tried crash, and the message in dmesg looks
> > > like this:
> > > [   39.510667] CPU: 0 PID: 1857 Comm: mytime Not tainted 4.15.0-rc7-00028-g45e0659df4d9 #41
> > > [   39.510712] Hardware name: linux,dummy-virt (DT)
> > > [   39.510829] pstate: 00000000 (nzcv daif -PAN -UAO)
> > > [   39.511101] pc : 0x33488e28
> > > [   39.511125] lr : 0x33488e28
> > > [   39.511138] sp : 00000000fffef670
> > > [   39.511158] x29: 000000005a536c33 x28: 0000000000000000 
> > > [   39.511211] x27: 0000000000000000 x26: 0000000000000000 
> > > [   39.511235] x25: 0000000000000000 x24: 0000000000000000 
> > > [   39.511257] x23: 0000000000466000 x22: 0000000000000000 
> > > [   39.511278] x21: 0000000000000000 x20: 000000000047f2a8 
> > > [   39.511300] x19: 0000000000000000 x18: 0000000000000001 
> > > [   39.511321] x17: 0000000000001000 x16: 0000000000001030 
> > > [   39.511342] x15: 0000000000554e47 x14: 0000000000000001 
> > > [   39.511364] x13: 0000000000000004 x12: 000000000000003c 
> > > [   39.511385] x11: 0000100000000000 x10: 0800000000000000 
> > > [   39.511406] x9 : 0fffffffffffffff x8 : 000000000000007c 
> > > [   39.511427] x7 : 0000000000000077 x6 : 0000000000000041 
> > > [   39.511448] x5 : 0000000000000411 x4 : 00000000fbad2488 
> > > [   39.511468] x3 : 0000000000000001 x2 : 0000000000497950 
> > > [   39.511489] x1 : 0000000000497550 x0 : 0000000000000001
> > 
> > Hi Dave,
> > 
> > I fixed the crash. It was my local problem.
> 
> Ah, right :)
> 
> I'll take a look at your code anyway in case there's something
> else one of us didn't think of.

Thanks, Dave.

This is the branch:
https://github.com/norov/linux/tree/ilp32-4.15-rc7

SVE-related changes are mostly in patches:
arm64: ilp32: introduce ilp32-specific handlers for sigframe and ucontext
arm64: signal32: move ilp32 and aarch32 common code to separated file
arm64: signal: share lp64 signal structures and routines to ilp32
arm64: ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it

Yury

Re: [PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

[Dave Martin]

On Tue, Jan 16, 2018 at 01:11:49PM +0300, Yury Norov wrote:
> On Mon, Jan 15, 2018 at 05:22:01PM +0000, Dave Martin wrote:

[...]

> > I'll take a look at your code anyway in case there's something
> > else one of us didn't think of.
> 
> Thanks, Dave.
> 
> This is the branch:
> https://github.com/norov/linux/tree/ilp32-4.15-rc7
> 
> SVE-related changes are mostly in patches:
> arm64: ilp32: introduce ilp32-specific handlers for sigframe and ucontext
> arm64: signal32: move ilp32 and aarch32 common code to separated file
> arm64: signal: share lp64 signal structures and routines to ilp32
> arm64: ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it

Thanks for the pointer.

Quick review of the relevant patches below.

> From 6f566a512cbac378ccee66094b5f9124b6069275 Mon Sep 17 00:00:00 2001
> From: Andrew Pinski <apinski@cavium.com>
> Date: Tue, 24 May 2016 03:04:47 +0300
> Subject: [PATCH 17/24] arm64: ilp32: add sys_ilp32.c and a separate table (in
>  entry.S) to use it
> 
> Add a separate syscall-table for ILP32, which dispatches either to native
> LP64 system call implementation or to compat-syscalls, as appropriate.
> 
> Signed-off-by: Andrew Pinski <Andrew.Pinski@caviumnetworks.com>
> Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
> Signed-off-by: Bamvor Jian Zhang <bamvor.zhangjian@linaro.org>

[...]

> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 778726d..d2d7336 100644

[...]

> @@ -864,14 +882,15 @@ ENDPROC(ret_to_user)
>  el0_svc:
>  	ldr	x16, [tsk, #TSK_TI_FLAGS]	// load thread flags
>  	adrp	stbl, sys_call_table		// load syscall table pointer
> +	ldr	x19, [tsk, #TSK_TI_FLAGS]
>  	mov	wscno, w8			// syscall number in w8
>  	mov	wsc_nr, #__NR_syscalls
>  
>  #ifdef CONFIG_ARM64_SVE
>  alternative_if_not ARM64_SVE
> -	b	el0_svc_naked
> +	b	el0_svc_select_table
>  alternative_else_nop_endif
> -	tbz	x16, #TIF_SVE, el0_svc_naked	// Skip unless TIF_SVE set:
> +	tbz	x16, #TIF_SVE, el0_svc_select_table	// Skip unless TIF_SVE set:
>  	bic	x16, x16, #_TIF_SVE		// discard SVE state
>  	str	x16, [tsk, #TSK_TI_FLAGS]
>  
> @@ -887,12 +906,19 @@ alternative_else_nop_endif
>  	msr	cpacr_el1, x9			// synchronised by eret to el0
>  #endif
>  
> +el0_svc_select_table:
> +#ifdef CONFIG_ARM64_ILP32
> +	tst	x19, #_TIF_32BIT_AARCH64
> +	b.eq	el0_svc_naked			// We are using LP64  syscall table

Can tbz be used here?

> +	adrp	stbl, sys_call_ilp32_table	// load ilp32 syscall table pointer
> +	delouse_input_regs
> +#endif
>  el0_svc_naked:					// compat entry point
>  	stp	x0, xscno, [sp, #S_ORIG_X0]	// save the original x0 and syscall number

[...]


> From 6e55e1c381aa4b6e10ac5eda0a587adf5558f438 Mon Sep 17 00:00:00 2001
> From: Yury Norov <ynorov@caviumnetworks.com>
> Date: Mon, 26 Jun 2017 19:11:58 +0300
> Subject: [PATCH 18/24] arm64: signal: share lp64 signal structures and
>  routines to ilp32

Nit: Please ensure that the commit message makes sense without the
subject line, so that users of Mutt etc., can see all necessary context
in the message body when drafting a reply.

> After that, it will be possible to reuse it in ilp32.
> 
> Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>


[...]

> +#define parse_user_sigcontext(user, sf)					\
> +	__parse_user_sigcontext(user, &(sf)->uc.uc_mcontext, sf)

Nit: can this #define be kept next to the function it wraps?

> +
> +struct user_ctxs {
> +	struct fpsimd_context __user *fpsimd;
> +	struct sve_context __user *sve;
> +};
> +
> +struct frame_record {
> +	u64 fp;
> +	u64 lr;
> +};
> +struct rt_sigframe_user_layout;
> +
> +int setup_extra_context(char __user *sfp, unsigned long users, char __user *userp);
> +int __parse_user_sigcontext(struct user_ctxs *user,
> +				   struct sigcontext __user const *sc,
> +				   void __user const *sigframe_base);

[...]

> diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c

[...]

> +int setup_extra_context(char __user *sfp, unsigned long users, char __user *userp)
> +{
> +	int err =0;

Nit: missing space.

Also, while "user<blah>" seemed OK as a local variable name, it now
looks rather obscure as a function parameter name, since the meaning of
the parameter is not so obvious.

"users" is really the total sigframe size, so "sf_size" may be a
reasonable name.

"extrap" might be a slightly better name for "userp", since this is not
a general-purpose cursor and must point to the base address computed for
the extra_context block.

(I'm open to better suggestions though.)

> +	struct extra_context __user *extra;
> +	struct _aarch64_ctx __user *end;
> +	u64 extra_datap;
> +	u32 extra_size;
> +
> +	extra = (struct extra_context __user *)userp;
> +	userp += EXTRA_CONTEXT_SIZE;
> +
> +	end = (struct _aarch64_ctx __user *)userp;
> +	userp += TERMINATOR_SIZE;
> +
> +	/*
> +	 * extra_datap is just written to the signal frame.
> +	 * The value gets cast back to a void __user *
> +	 * during sigreturn.
> +	 */
> +	extra_datap = (__force u64)userp;
> +	extra_size = sfp + round_up(users, 16) - userp;
> +
> +	__put_user_error(EXTRA_MAGIC, &extra->head.magic, err);
> +	__put_user_error(EXTRA_CONTEXT_SIZE, &extra->head.size, err);
> +	__put_user_error(extra_datap, &extra->datap, err);
> +	__put_user_error(extra_size, &extra->size, err);
> +
> +	/* Add the terminator */
> +	__put_user_error(0, &end->magic, err);
> +	__put_user_error(0, &end->size, err);
> +
> +	return err;
> +}

[...]

> @@ -652,39 +656,9 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user,
>  		err |= preserve_sve_context(sve_ctx);
>  	}
>  
> -	if (err == 0 && user->extra_offset) {
> -		char __user *sfp = (char __user *)user->sigframe;
> -		char __user *userp =
> -			apply_user_offset(user, user->extra_offset);
> -
> -		struct extra_context __user *extra;
> -		struct _aarch64_ctx __user *end;
> -		u64 extra_datap;
> -		u32 extra_size;
> -
> -		extra = (struct extra_context __user *)userp;
> -		userp += EXTRA_CONTEXT_SIZE;
> -
> -		end = (struct _aarch64_ctx __user *)userp;
> -		userp += TERMINATOR_SIZE;
> -
> -		/*
> -		 * extra_datap is just written to the signal frame.
> -		 * The value gets cast back to a void __user *
> -		 * during sigreturn.
> -		 */
> -		extra_datap = (__force u64)userp;
> -		extra_size = sfp + round_up(user->size, 16) - userp;
> -
> -		__put_user_error(EXTRA_MAGIC, &extra->head.magic, err);
> -		__put_user_error(EXTRA_CONTEXT_SIZE, &extra->head.size, err);
> -		__put_user_error(extra_datap, &extra->datap, err);
> -		__put_user_error(extra_size, &extra->size, err);
> -
> -		/* Add the terminator */
> -		__put_user_error(0, &end->magic, err);
> -		__put_user_error(0, &end->size, err);
> -	}
> +	if (err == 0 && user->extra_offset)
> +		setup_extra_context((char *) user->sigframe, user->size,
> +			(char *) apply_user_offset(user, user->extra_offset));

Nit: no space after (type *) please.

Also, can we have (char __user *)?  This is more "correct" because these
arguments are not valid kernel pointers.  Keeping the __user may avoid
sparse warnings.  (I've not tried to build the code yet, so I don't know
whether sparse actually complains about __user being cast on and off
here.)

[...]


> From 735931121210a692038859448bf9f4ac5905eb73 Mon Sep 17 00:00:00 2001
> From: Yury Norov <ynorov@caviumnetworks.comk>
> Date: Tue, 24 May 2016 03:04:50 +0300
> Subject: [PATCH 20/24] arm64: ilp32: introduce ilp32-specific handlers for
>  sigframe and ucontext
>
> ILP32 uses AARCH32 compat structures and syscall handlers for signals.
> But ILP32 struct rt_sigframe  and ucontext differs from both LP64 and
> AARCH32. So some specific mechanism is needed to take care of it.
>
> Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>

The code here looks reasonably correct, but there is a lot of
unnecessary duplication of code that should really be common.

This code is security-critical and tricky to get right, so we don't
want to have to maintain and test two independent implementations of
anything if we can possibly avoid it.

I think there may at least one change in the LP64 code that has not
been propagated here (the call to
fpsimd_signal_preserve_current_state() in setup_rt_frame()).  There
will likely be more such cases in the future.

[...]

diff --git a/arch/arm64/kernel/signal_ilp32.c b/arch/arm64/kernel/signal_ilp32.c
new file mode 100644
index 0000000..a1cb058
> --- /dev/null
> +++ b/arch/arm64/kernel/signal_ilp32.c

[...]

> +#define BASE_SIGFRAME_SIZE round_up(sizeof(struct ilp32_rt_sigframe), 16)
> +
> +struct ilp32_ucontext {
> +        u32		uc_flags;
> +        u32		uc_link;
> +        compat_stack_t  uc_stack;
> +        compat_sigset_t uc_sigmask;
> +        /* glibc uses a 1024-bit sigset_t */
> +        __u8            __unused[1024 / 8 - sizeof(compat_sigset_t)];
> +        /* last for future expansion */
> +        struct sigcontext uc_mcontext;
> +};
> +
> +struct ilp32_rt_sigframe {
> +	struct compat_siginfo info;
> +	struct ilp32_ucontext uc;
> +};
> +
> +struct ilp32_rt_sigframe_user_layout {
> +	struct ilp32_rt_sigframe __user *sigframe;

I think much of the duplication here flows from the fact that this
struct currently has a different type for ILP32 versus LP64, even
though all the important contents of the structure are equivalent for
the two cases.

Can we replace the sigframe pointer with a void __user *, or union {
	struct rt_sigframe __user *;
	struct ilp32_rt_sigframe __user *;
} ?

Putting a pointer to sigcontext in here may also help, since it
looks the same for both cases: only its location changes (I think).


This would allow us to use the same sigframe_user_layout struct for
the lp64 and ilp32 cases, which will make it easier to share code.

The __reserved[] and extra_context blocks and the records in them
should be handled identically for the two ABIs: the only thing that
should differ is the offset of __reserved[] in the complete signal
frame.


We should try hard to make as much code as possible generic here.  I
won't comment on the individual functions for now: I think they can
all be mostly or completely eliminated.

[...]

Cheers
---Dave