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From: Wu Hao <hao.wu@intel.com>
To: Alan Tull <atull@kernel.org>
Cc: Moritz Fischer <mdf@kernel.org>,
	linux-fpga@vger.kernel.org,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-api@vger.kernel.org, "Kang, Luwei" <luwei.kang@intel.com>,
	"Zhang, Yi Z" <yi.z.zhang@intel.com>,
	Tim Whisonant <tim.whisonant@intel.com>,
	Enno Luebbers <enno.luebbers@intel.com>,
	Shiva Rao <shiva.rao@intel.com>,
	Christopher Rauer <christopher.rauer@intel.com>,
	Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: Re: [PATCH v5 07/28] fpga: dfl: add chardev support for feature devices
Date: Wed, 6 Jun 2018 20:24:57 +0800	[thread overview]
Message-ID: <20180606122457.GB7681@hao-dev> (raw)
In-Reply-To: <CANk1AXRQx=QtwmSKuWiGprMcfjNnUWcBHNy-hTfP+JaQZsJLLA@mail.gmail.com>

On Tue, Jun 05, 2018 at 03:21:48PM -0500, Alan Tull wrote:
> On Tue, May 1, 2018 at 9:50 PM, Wu Hao <hao.wu@intel.com> wrote:
> 
> Hi Hao,
> 
> > For feature devices drivers, both the FPGA Management Engine (FME) and
> > Accelerated Function Unit (AFU) driver need to expose user interfaces via
> > the device file, for example, mmap and ioctls.
> >
> > This patch adds chardev support in the dfl driver for feature devices,
> > FME and AFU. It reserves the chardev regions for FME and AFU, and provide
> > interfaces for FME and AFU driver to register their device file operations.
> >
> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> > Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > Signed-off-by: Wu Hao <hao.wu@intel.com>
> > ---
> > v2: rebased
> > v3: move chardev support to fpga-dfl framework
> > v4: rebase, and add more comments in code.
> > v5: rebase, and add dfl_ prefix to APIs and data structures.
> > ---
> >  drivers/fpga/dfl.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
> >  drivers/fpga/dfl.h |  14 ++++++++
> >  2 files changed, 117 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> > index c1462e9..18aba02 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -74,6 +74,96 @@ static enum dfl_id_type feature_dev_id_type(struct platform_device *pdev)
> >         return DFL_ID_MAX;
> >  }
> >
> > +struct dfl_chardev_info {
> > +       const char *name;
> > +       dev_t devt;
> > +};
> > +
> > +/* indexed by enum dfl_fpga_devt_type */
> > +struct dfl_chardev_info dfl_chrdevs[] = {
> > +       {.name = DFL_FPGA_FEATURE_DEV_FME},     /* DFL_FPGA_DEVT_FME */
> > +       {.name = DFL_FPGA_FEATURE_DEV_PORT},    /* DFL_FPGA_DEVT_AFU */
> > +};
> 
> If this were added in the initial dfl.c patch, it could be used by
> build_info_create_dev to get the name.

Sure, will fix this.

> 
> > +
> > +static void dfl_chardev_uinit(void)
> > +{
> > +       int i;
> > +
> > +       for (i = 0; i < DFL_FPGA_DEVT_MAX; i++)
> > +               if (MAJOR(dfl_chrdevs[i].devt)) {
> > +                       unregister_chrdev_region(dfl_chrdevs[i].devt,
> > +                                                MINORMASK);
> > +                       dfl_chrdevs[i].devt = MKDEV(0, 0);
> > +               }
> > +}
> > +
> > +static int dfl_chardev_init(void)
> > +{
> > +       int i, ret;
> > +
> > +       for (i = 0; i < DFL_FPGA_DEVT_MAX; i++) {
> > +               ret = alloc_chrdev_region(&dfl_chrdevs[i].devt, 0, MINORMASK,
> > +                                         dfl_chrdevs[i].name);
> > +               if (ret)
> > +                       goto exit;
> > +       }
> > +
> > +       return 0;
> > +
> > +exit:
> > +       dfl_chardev_uinit();
> > +       return ret;
> > +}
> > +
> > +static dev_t dfl_get_devt(enum dfl_fpga_devt_type type, int id)
> > +{
> > +       WARN_ON(type >= DFL_FPGA_DEVT_MAX);
> > +
> > +       return MKDEV(MAJOR(dfl_chrdevs[type].devt), id);
> > +}
> > +
> > +/**
> > + * dfl_fpga_register_dev_ops - register cdev ops for feature dev
> > + *
> > + * @pdev: feature dev.
> > + * @fops: file operations for feature dev's cdev.
> > + * @owner: owning module/driver.
> > + *
> > + * Return: 0 on success, negative error code otherwise.
> > + */
> > +int dfl_fpga_register_dev_ops(struct platform_device *pdev,
> > +                             const struct file_operations *fops,
> > +                             struct module *owner)
> > +{
> > +       struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > +
> > +       cdev_init(&pdata->cdev, fops);
> > +       pdata->cdev.owner = owner;
> > +
> > +       /*
> > +        * set parent to the feature device so that its refcount is
> > +        * decreased after the last refcount of cdev is gone, that
> > +        * makes sure the feature device is valid during device
> > +        * file's life-cycle.
> > +        */
> > +       pdata->cdev.kobj.parent = &pdev->dev.kobj;
> > +
> > +       return cdev_add(&pdata->cdev, pdev->dev.devt, 1);
> > +}
> > +EXPORT_SYMBOL_GPL(dfl_fpga_register_dev_ops);
> > +
> > +/**
> > + * dfl_fpga_unregister_dev_ops - unregister cdev ops for feature dev
> > + * @pdev: feature dev.
> > + */
> > +void dfl_fpga_unregister_dev_ops(struct platform_device *pdev)
> > +{
> > +       struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > +
> > +       cdev_del(&pdata->cdev);
> > +}
> > +EXPORT_SYMBOL_GPL(dfl_fpga_unregister_dev_ops);
> > +
> >  /**
> >   * struct build_feature_devs_info - info collected during feature dev build.
> >   *
> > @@ -208,9 +298,13 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
> >                       enum dfl_id_type type, const char *name,
> >                       void __iomem *ioaddr)
> >  {
> > +       enum dfl_fpga_devt_type devt_type = DFL_FPGA_DEVT_FME;
> >         struct platform_device *fdev;
> >         int ret;
> >
> > +       if (type == PORT_ID)
> > +               devt_type = DFL_FPGA_DEVT_PORT;
> > +
> >         /* we will create a new device, commit current device first */
> >         ret = build_info_commit_dev(binfo);
> >         if (ret)
> > @@ -234,6 +328,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
> >                 return fdev->id;
> >
> >         fdev->dev.parent = &binfo->cdev->region->dev;
> > +       fdev->dev.devt = dfl_get_devt(devt_type, fdev->id);
> >
> >         return 0;
> >  }
> > @@ -702,13 +797,20 @@ void dfl_fpga_remove_feature_devs(struct dfl_fpga_cdev *cdev)
> >
> >  static int __init dfl_fpga_init(void)
> >  {
> > +       int ret;
> > +
> >         dfl_ids_init();
> >
> > -       return 0;
> > +       ret = dfl_chardev_init();
> > +       if (ret)
> > +               dfl_ids_destroy();
> > +
> > +       return ret;
> >  }
> >
> >  static void __exit dfl_fpga_exit(void)
> >  {
> > +       dfl_chardev_uinit();
> >         dfl_ids_destroy();
> >  }
> >
> > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> > index 2ede915..5fcb1a1 100644
> > --- a/drivers/fpga/dfl.h
> > +++ b/drivers/fpga/dfl.h
> > @@ -15,6 +15,7 @@
> >  #define __FPGA_DFL_H
> >
> >  #include <linux/bitfield.h>
> > +#include <linux/cdev.h>
> >  #include <linux/delay.h>
> >  #include <linux/fs.h>
> >  #include <linux/iopoll.h>
> > @@ -150,6 +151,7 @@ struct dfl_feature {
> >   *
> >   * @node: node to link feature devs to container device's port_dev_list.
> >   * @lock: mutex to protect platform data.
> > + * @cdev: cdev of feature dev.
> >   * @dev: ptr to platform device linked with this platform data.
> >   * @dfl_cdev: ptr to container device.
> >   * @disable_count: count for port disable.
> > @@ -159,6 +161,7 @@ struct dfl_feature {
> >  struct dfl_feature_platform_data {
> >         struct list_head node;
> >         struct mutex lock;
> > +       struct cdev cdev;
> >         struct platform_device *dev;
> >         struct dfl_fpga_cdev *dfl_cdev;
> >         unsigned int disable_count;
> > @@ -176,6 +179,17 @@ static inline int dfl_feature_platform_data_size(const int num)
> >                 num * sizeof(struct dfl_feature);
> >  }
> >
> > +enum dfl_fpga_devt_type {
> > +       DFL_FPGA_DEVT_FME,
> > +       DFL_FPGA_DEVT_PORT,
> > +       DFL_FPGA_DEVT_MAX,
> > +};
> 
> Could you move this enum to be close to other similar enums (like
> dfl_id_type)?  The dfl code has a few enums that are similar, and may
> need updating (or not) as feature are added.  Putting them close
> together with appropriate comments would be helpful to keep them all
> straight.

Agree, I will fix this in v6.
Thanks for the review.

Hao

  reply	other threads:[~2018-06-06 12:24 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-02  2:50 [PATCH v5 00/28] FPGA Device Feature List (DFL) Device Drivers Wu Hao
2018-05-02  2:50 ` [PATCH v5 01/28] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview Wu Hao
2018-06-06 16:16   ` Alan Tull
2018-06-07  2:00     ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 02/28] fpga: mgr: add region_id to fpga_image_info Wu Hao
2018-05-02  2:50 ` [PATCH v5 03/28] fpga: mgr: add status for fpga-manager Wu Hao
2018-05-02  2:50 ` [PATCH v5 04/28] fpga: mgr: add compat_id support Wu Hao
2018-05-07 21:09   ` Alan Tull
2018-05-21  3:03     ` Wu Hao
2018-05-21 17:33       ` Alan Tull
2018-05-22  9:39         ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 05/28] fpga: region: " Wu Hao
2018-05-07 21:09   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 06/28] fpga: add device feature list support Wu Hao
2018-06-05 20:21   ` Alan Tull
2018-06-06 12:22     ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 07/28] fpga: dfl: add chardev support for feature devices Wu Hao
2018-06-05 20:21   ` Alan Tull
2018-06-06 12:24     ` Wu Hao [this message]
2018-06-07 18:03       ` Alan Tull
2018-06-08  0:11         ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 08/28] fpga: dfl: add dfl_fpga_cdev_find_port Wu Hao
2018-05-02  2:50 ` [PATCH v5 09/28] fpga: dfl: add feature device infrastructure Wu Hao
2018-06-05 21:14   ` Alan Tull
2018-06-06 12:33     ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 10/28] fpga: dfl: add dfl_fpga_port_ops support Wu Hao
2018-06-05 21:24   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 11/28] fpga: dfl: add dfl_fpga_check_port_id function Wu Hao
2018-06-05 21:25   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 12/28] fpga: add FPGA DFL PCIe device driver Wu Hao
2018-05-02  2:50 ` [PATCH v5 13/28] fpga: dfl-pci: add enumeration for feature devices Wu Hao
2018-05-02  2:50 ` [PATCH v5 14/28] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2018-06-06 16:08   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 15/28] fpga: dfl: fme: add header sub feature support Wu Hao
2018-05-02  2:50 ` [PATCH v5 16/28] fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-05-02  2:50 ` [PATCH v5 17/28] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2018-06-06 16:08   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 18/28] fpga: dfl: add fpga manager platform driver for FME Wu Hao
2018-06-06 15:52   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 19/28] fpga: dfl: fme-mgr: add compat_id support Wu Hao
2018-05-07 21:12   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 20/28] fpga: dfl: add fpga bridge platform driver for FME Wu Hao
2018-05-23 15:15   ` Alan Tull
2018-05-23 15:28     ` Wu Hao
2018-05-23 21:06       ` Alan Tull
2018-05-23 23:42         ` Wu Hao
2018-05-24 17:26           ` Alan Tull
2018-05-24 23:59             ` Wu Hao
2018-05-02  2:50 ` [PATCH v5 21/28] fpga: dfl: add fpga region " Wu Hao
2018-05-02  2:50 ` [PATCH v5 22/28] fpga: dfl: fme-region: add support for compat_id Wu Hao
2018-05-07 21:12   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 23/28] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2018-05-02  2:50 ` [PATCH v5 24/28] fpga: dfl: afu: add port ops support Wu Hao
2018-06-06 15:57   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 25/28] fpga: dfl: afu: add header sub feature support Wu Hao
2018-05-02  2:50 ` [PATCH v5 26/28] fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-05-02  2:50 ` [PATCH v5 27/28] fpga: dfl: afu: add afu sub feature support Wu Hao
2018-06-06 16:04   ` Alan Tull
2018-05-02  2:50 ` [PATCH v5 28/28] fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2018-06-06 16:09   ` Alan Tull
2018-05-03 21:14 ` [PATCH v5 00/28] FPGA Device Feature List (DFL) Device Drivers Alan Tull
2018-05-04  0:15   ` Wu Hao

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