linux-api.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Moritz Fischer <mdf@kernel.org>
To: Wu Hao <hao.wu@intel.com>
Cc: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
	luwei.kang@intel.com, yi.z.zhang@intel.com,
	Tim Whisonant <tim.whisonant@intel.com>,
	Enno Luebbers <enno.luebbers@intel.com>,
	Shiva Rao <shiva.rao@intel.com>,
	Christopher Rauer <christopher.rauer@intel.com>,
	Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: Re: [PATCH v6 12/29] fpga: add FPGA DFL PCIe device driver
Date: Wed, 13 Jun 2018 06:54:20 -0700	[thread overview]
Message-ID: <20180613135420.GB3866@archbook> (raw)
In-Reply-To: <1528798243-2029-13-git-send-email-hao.wu@intel.com>

On Tue, Jun 12, 2018 at 06:10:26PM +0800, Wu Hao wrote:
> From: Zhang Yi <yi.z.zhang@intel.com>
> 
> This patch implements the basic framework of the driver for FPGA PCIe
> device which implements the Device Feature List (DFL) in its MMIO space.
> This driver is verified on Intel(R) PCIe based FPGA DFL devices, including
> both integrated (e.g Intel Server Platform with In-package FPGA) and
> discrete (e.g Intel FPGA PCIe Acceleration Cards) solutions.
> 
> Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v2: move the code to drivers/fpga folder as suggested by Alan Tull.
>     switch to GPLv2 license.
>     fix comments from Moritz Fischer.
> v3: switch to pci_set_dma_mask/consistent_dma_mask() function.
>     remove pci_save_state() in probe function.
>     rename driver to INTEL_FPGA_DFL_PCI and intel-dfl-pci.c to indicate
>     this driver supports Intel FPGA PCI devices which implement DFL.
>     improve Kconfig description for INTEL_FPGA_DFL_PCI
> v4: rename to FPGA_DFL_PCI (dfl-pci.c) for better reuse.
>     fix SPDX license issue.
> v5: use module_pci_driver() instead.
>     add Acked-by from Alan and Moritz.
> v6: rebase and unify naming in Kconfig
> ---
>  drivers/fpga/Kconfig   |  15 +++++++
>  drivers/fpga/Makefile  |   3 ++
>  drivers/fpga/dfl-pci.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 132 insertions(+)
>  create mode 100644 drivers/fpga/dfl-pci.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 4052532..5faab48 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,4 +146,19 @@ config FPGA_DFL
>  	  Gate Array (FPGA) solutions which implement Device Feature List.
>  	  It provides enumeration APIs, and feature device infrastructure.
>  
> +config FPGA_DFL_PCI
> +	tristate "FPGA DFL PCIe Device Driver"
> +	depends on PCI && FPGA_DFL
> +	help
> +	  Select this option to enable PCIe driver for PCIe based
> +	  Field-Programmable Gate Array (FPGA) solutions which implemented
> +	  the Device Feature List (DFL). This driver provides interfaces
> +	  for userspace applications to configure, enumerate, open and access
> +	  FPGA accelerators on the FPGA DFL devices, enables system level
> +	  management functions such as FPGA partial reconfiguration, power
> +	  management, and virtualization with DFL framework and DFL feature
> +	  device drivers.
> +
> +	  To compile this as a module, choose M here.
> +
>  endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 7a7a117..02e0253 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -31,3 +31,6 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
>  
>  # FPGA Device Feature List Support
>  obj-$(CONFIG_FPGA_DFL)			+= dfl.o
> +
> +# Drivers for FPGAs which implement DFL
> +obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> new file mode 100644
> index 0000000..5824c5e
> --- /dev/null
> +++ b/drivers/fpga/dfl-pci.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for FPGA Device Feature List (DFL) PCIe device
> + *
> + * Copyright (C) 2017-2018 Intel Corporation, Inc.
> + *
> + * Authors:
> + *   Zhang Yi <Yi.Z.Zhang@intel.com>
> + *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
> + *   Joseph Grecco <joe.grecco@intel.com>
> + *   Enno Luebbers <enno.luebbers@intel.com>
> + *   Tim Whisonant <tim.whisonant@intel.com>
> + *   Ananda Ravuri <ananda.ravuri@intel.com>
> + *   Henry Mitchel <henry.mitchel@intel.com>
> + */
> +
> +#include <linux/pci.h>
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/stddef.h>
> +#include <linux/errno.h>
> +#include <linux/aer.h>
> +
> +#define DRV_VERSION	"0.8"
> +#define DRV_NAME	"dfl-pci"
> +
> +/* PCI Device ID */
> +#define PCIE_DEVICE_ID_PF_INT_5_X	0xBCBD
> +#define PCIE_DEVICE_ID_PF_INT_6_X	0xBCC0
> +#define PCIE_DEVICE_ID_PF_DSC_1_X	0x09C4
> +/* VF Device */
> +#define PCIE_DEVICE_ID_VF_INT_5_X	0xBCBF
> +#define PCIE_DEVICE_ID_VF_INT_6_X	0xBCC1
> +#define PCIE_DEVICE_ID_VF_DSC_1_X	0x09C5
> +
> +static struct pci_device_id cci_pcie_id_tbl[] = {
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
> +	{0,}
> +};
> +MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
> +
> +static
> +int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
> +{
> +	int ret;
> +
> +	ret = pci_enable_device(pcidev);

Any reason we cannot use pcim_enable_device() here?
> +	if (ret < 0) {
> +		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
> +		return ret;
> +	}
> +
> +	ret = pci_enable_pcie_error_reporting(pcidev);
> +	if (ret && ret != -EINVAL)
> +		dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
> +
> +	ret = pci_request_regions(pcidev, DRV_NAME);
> +	if (ret) {
> +		dev_err(&pcidev->dev, "Failed to request regions.\n");
> +		goto disable_error_report_exit;
> +	}
> +
> +	pci_set_master(pcidev);
> +
> +	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
> +		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
> +		if (ret)
> +			goto release_region_exit;
> +	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
> +		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
> +		if (ret)
> +			goto release_region_exit;
> +	} else {
> +		ret = -EIO;
> +		dev_err(&pcidev->dev, "No suitable DMA support available.\n");
> +		goto release_region_exit;
> +	}
> +
> +	/* TODO: create and add the platform device per feature list */
> +	return 0;
> +
> +release_region_exit:
> +	pci_release_regions(pcidev);
> +disable_error_report_exit:
> +	pci_disable_pcie_error_reporting(pcidev);
> +	pci_disable_device(pcidev);
> +	return ret;
> +}
> +
> +static void cci_pci_remove(struct pci_dev *pcidev)
> +{
> +	pci_release_regions(pcidev);
> +	pci_disable_pcie_error_reporting(pcidev);
> +	pci_disable_device(pcidev);
> +}
> +
> +static struct pci_driver cci_pci_driver = {
> +	.name = DRV_NAME,
> +	.id_table = cci_pcie_id_tbl,
> +	.probe = cci_pci_probe,
> +	.remove = cci_pci_remove,
> +};
> +
> +module_pci_driver(cci_pci_driver);
> +
> +MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.3.1
> 

Cheers,
Moritz

  parent reply	other threads:[~2018-06-13 13:54 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 10:10 [PATCH v6 00/29] FPGA Device Feature List (DFL) Device Drivers Wu Hao
2018-06-12 10:10 ` [PATCH v6 01/29] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview Wu Hao
2018-06-12 10:10 ` [PATCH v6 02/29] fpga: mgr: add region_id to fpga_image_info Wu Hao
2018-06-12 10:10 ` [PATCH v6 03/29] fpga: mgr: add status for fpga-manager Wu Hao
2018-06-12 15:57   ` Alan Tull
2018-06-12 10:10 ` [PATCH v6 04/29] fpga: mgr: add compat_id support Wu Hao
2018-06-12 10:10 ` [PATCH v6 05/29] fpga: region: " Wu Hao
2018-06-13 14:44   ` Moritz Fischer
2018-06-12 10:10 ` [PATCH v6 06/29] fpga: add device feature list support Wu Hao
2018-06-12 15:27   ` Randy Dunlap
2018-06-12 15:42   ` Alan Tull
2018-06-12 10:10 ` [PATCH v6 07/29] fpga: dfl: add chardev support for feature devices Wu Hao
2018-06-12 15:55   ` Alan Tull
2018-06-12 10:10 ` [PATCH v6 08/29] fpga: dfl: add dfl_fpga_cdev_find_port Wu Hao
2018-06-12 10:10 ` [PATCH v6 09/29] fpga: dfl: add feature device infrastructure Wu Hao
2018-06-12 10:10 ` [PATCH v6 10/29] fpga: dfl: add dfl_fpga_port_ops support Wu Hao
2018-06-12 10:10 ` [PATCH v6 11/29] fpga: dfl: add dfl_fpga_check_port_id function Wu Hao
2018-06-12 10:10 ` [PATCH v6 12/29] fpga: add FPGA DFL PCIe device driver Wu Hao
2018-06-12 15:27   ` Randy Dunlap
2018-06-12 23:42     ` Wu Hao
2018-06-13 13:54   ` Moritz Fischer [this message]
2018-06-13 16:34     ` Wu Hao
2018-06-12 10:10 ` [PATCH v6 13/29] fpga: dfl-pci: add enumeration for feature devices Wu Hao
2018-06-12 10:10 ` [PATCH v6 14/29] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2018-06-12 15:27   ` Randy Dunlap
2018-06-13 14:13   ` Moritz Fischer
2018-06-12 10:10 ` [PATCH v6 15/29] fpga: dfl: fme: add header sub feature support Wu Hao
2018-06-12 10:10 ` [PATCH v6 16/29] fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-06-12 10:10 ` [PATCH v6 17/29] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2018-06-14  1:07   ` Moritz Fischer
2018-06-14 16:33     ` Alan Tull
2018-06-15  5:52       ` Wu Hao
2018-06-12 10:10 ` [PATCH v6 18/29] fpga: dfl: add fpga manager platform driver for FME Wu Hao
2018-06-14  1:16   ` Moritz Fischer
2018-06-14 13:50     ` Wu Hao
2018-06-12 10:10 ` [PATCH v6 19/29] fpga: dfl: fme-mgr: add compat_id support Wu Hao
2018-06-13 20:08   ` Moritz Fischer
2018-06-12 10:10 ` [PATCH v6 20/29] fpga: dfl: add fpga bridge platform driver for FME Wu Hao
2018-06-12 10:10 ` [PATCH v6 21/29] fpga: dfl: add fpga region " Wu Hao
2018-06-12 10:10 ` [PATCH v6 22/29] fpga: dfl: fme-region: add support for compat_id Wu Hao
2018-06-13 14:18   ` Moritz Fischer
2018-06-12 10:10 ` [PATCH v6 23/29] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2018-06-12 15:27   ` Randy Dunlap
2018-06-12 10:10 ` [PATCH v6 24/29] fpga: dfl: afu: add port ops support Wu Hao
2018-06-12 10:10 ` [PATCH v6 25/29] fpga: dfl: afu: add header sub feature support Wu Hao
2018-06-12 10:10 ` [PATCH v6 26/29] fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-06-12 10:10 ` [PATCH v6 27/29] fpga: dfl: afu: add afu sub feature support Wu Hao
2018-06-12 10:10 ` [PATCH v6 28/29] fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2018-06-12 10:10 ` [PATCH v6 29/29] MAINTAINERS: add entry for FPGA DFL drivers Wu Hao
2018-06-13  0:56   ` Alan Tull
2018-06-13 13:50   ` Moritz Fischer
2018-06-12 17:33 ` [PATCH v6 00/29] FPGA Device Feature List (DFL) Device Drivers Alan Tull
2018-06-12 23:37   ` Wu Hao

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180613135420.GB3866@archbook \
    --to=mdf@kernel.org \
    --cc=atull@kernel.org \
    --cc=christopher.rauer@intel.com \
    --cc=enno.luebbers@intel.com \
    --cc=guangrong.xiao@linux.intel.com \
    --cc=hao.wu@intel.com \
    --cc=linux-api@vger.kernel.org \
    --cc=linux-fpga@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=luwei.kang@intel.com \
    --cc=shiva.rao@intel.com \
    --cc=tim.whisonant@intel.com \
    --cc=yi.z.zhang@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).