From: Wu Hao <hao.wu@intel.com>
To: Scott Wood <swood@redhat.com>
Cc: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
Ananda Ravuri <ananda.ravuri@intel.com>,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR
Date: Wed, 27 Mar 2019 13:46:37 +0800 [thread overview]
Message-ID: <20190327054637.GC20968@hao-dev> (raw)
In-Reply-To: <127a9356a7bf597d35dd361f2b16bf80460f0370.camel@redhat.com>
On Mon, Mar 25, 2019 at 05:53:50PM -0500, Scott Wood wrote:
> On Mon, 2019-03-25 at 11:07 +0800, Wu Hao wrote:
> > @@ -200,21 +228,32 @@ static int fme_mgr_write(struct fpga_manager *mgr,
> > pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT,
> > pr_status);
> > }
> >
> > - if (count < 4) {
> > + if (count < priv->pr_datawidth) {
> > dev_err(dev, "Invalid PR bitstream size\n");
> > return -EINVAL;
>
> Shouldn't this have become a WARN_ON in patch 2 given that the kernel
> already pads the buffer?
Thanks a lot for the review and comments.
I agree. it's better to use WARN_ON this place.
>
> > }
> >
> > - pr_data = 0;
> > - pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
> > - *(((u32 *)buf) + i));
> > - writeq(pr_data, fme_pr + FME_PR_DATA);
> > - count -= 4;
> > + switch (priv->pr_datawidth) {
> > + case 4:
> > + pr_data = 0;
> > + pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
> > + *((u32 *)buf));
>
> I know it's not new, but why not just "pr_data = FIELD..."? Const should
> also be preserved in the cast, and you can drop one set of parentheses.
Yes, agree, will fix this.
>
> > + writeq(pr_data, fme_pr + FME_PR_DATA);
> > + break;
> > + case 64:
> > + copy512((void *)buf, fme_pr + FME_PR_512_DATA);
> > + break;
>
> Unnecessary cast.
Will fix this.
>
> > + default:
> > + ret = -EFAULT;
> > + goto done;
>
> How is it EFAULT? Any other value for pr_datawidth should be WARN_ON
> since it's set by kernel code.
Agree, will fix this in the next version.
>
> > @@ -159,13 +161,10 @@ static int fme_pr(struct platform_device *pdev,
> > unsigned long arg)
> > fpga_bridges_put(®ion->bridge_list);
> >
> > put_device(®ion->dev);
> > -unlock_exit:
> > - mutex_unlock(&pdata->lock);
> > free_exit:
> > vfree(buf);
> > - if (copy_to_user((void __user *)arg, &port_pr, minsz))
> > - return -EFAULT;
> > -
>
> Why is the copy_to_user being removed?
This code is not needed at all but added by mistake i think.
Sorry, i should move these code into a separated patch with proper comments
to avoid confusion.
Thanks
Hao
>
> -Scott
next prev parent reply other threads:[~2019-03-27 5:46 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 3:07 [PATCH 00/17] add new features for FPGA DFL drivers Wu Hao
2019-03-25 3:07 ` [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-03-25 17:28 ` Alan Tull
2019-04-01 19:54 ` Moritz Fischer
2019-04-02 4:38 ` Wu Hao
2019-04-02 13:33 ` Moritz Fischer
2019-03-25 3:07 ` [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-03-25 17:50 ` Alan Tull
2019-03-26 0:28 ` Wu Hao
2019-03-28 18:50 ` Alan Tull
2019-03-25 3:07 ` [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-03-25 18:48 ` Alan Tull
2019-03-25 22:53 ` Scott Wood
2019-03-25 22:58 ` Scott Wood
2019-03-26 19:33 ` Alan Tull
2019-03-26 21:22 ` Scott Wood
2019-03-27 4:37 ` Wu Hao
2019-03-27 6:10 ` Scott Wood
2019-03-27 6:03 ` Wu Hao
2019-03-27 5:10 ` Wu Hao
2019-03-27 6:19 ` Scott Wood
2019-03-27 7:10 ` Wu Hao
2019-03-27 5:46 ` Wu Hao [this message]
2019-03-25 3:07 ` [PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-03-25 3:07 ` [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 06/17] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-03-28 17:13 ` Alan Tull
2019-03-25 3:07 ` [PATCH 08/17] fpga: dfl: afu: add userclock " Wu Hao
2019-04-01 21:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-04-02 15:09 ` Moritz Fischer
2019-04-11 20:55 ` Alan Tull
2019-03-25 3:07 ` [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-04-02 15:50 ` Moritz Fischer
2019-04-11 20:45 ` Alan Tull
2019-03-25 3:07 ` [PATCH 11/17] fpga: dfl: afu: add error reporting support Wu Hao
2019-04-09 20:57 ` Alan Tull
2019-04-10 1:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-04-02 15:07 ` Moritz Fischer
2019-04-11 20:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-04-09 21:05 ` Alan Tull
2019-03-25 3:07 ` [PATCH 14/17] fpga: dfl: fme: add thermal management support Wu Hao
2019-04-02 14:59 ` Moritz Fischer
2019-04-03 16:31 ` Wu Hao
2019-04-03 18:09 ` Moritz Fischer
2019-04-03 23:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 15/17] fpga: dfl: fme: add power " Wu Hao
2019-04-11 20:07 ` Alan Tull
2019-04-12 2:50 ` Wu Hao
2019-04-15 21:17 ` Alan Tull
2019-04-17 7:36 ` Wu Hao
2019-04-12 21:05 ` Moritz Fischer
2019-04-17 7:31 ` Wu Hao
2019-03-25 3:07 ` [PATCH 16/17] fpga: dfl: fme: add global error reporting support Wu Hao
2019-04-09 21:35 ` Alan Tull
2019-04-10 1:34 ` Wu Hao
2019-03-25 3:07 ` [PATCH 17/17] fpga: dfl: fme: add performance " Wu Hao
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