From: Andrew Murray <andrew.murray@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
libc-alpha@sourceware.org, Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
linux-api@vger.kernel.org, Phil Blundell <pb@pbcl.net>,
dave.martin@arm.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/7] arm64: Handle trapped DC CVADP
Date: Mon, 1 Apr 2019 11:45:09 +0100 [thread overview]
Message-ID: <20190401104515.39775-2-andrew.murray@arm.com> (raw)
In-Reply-To: <20190401104515.39775-1-andrew.murray@arm.com>
The ARMv8.5 DC CVADP instruction may be trapped to EL1 via
SCTLR_EL1.UCI therefore let's provide a handler for it.
Just like the CVAP instruction we use a 'sys' instruction instead of
the 'dc' alias to avoid build issues with older toolchains.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
---
arch/arm64/include/asm/esr.h | 3 ++-
arch/arm64/kernel/traps.c | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 52233f00d53d..07d5c026a0b3 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -198,9 +198,10 @@
/*
* User space cache operations have the following sysreg encoding
* in System instructions.
- * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
+ * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
*/
#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 8ad119c3f665..f66e1ddbe4a7 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -459,6 +459,9 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
__user_cache_maint("dc civac", address, ret);
break;
+ case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */
+ __user_cache_maint("sys 3, c7, c13, 1", address, ret);
+ break;
case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
__user_cache_maint("sys 3, c7, c12, 1", address, ret);
break;
--
2.21.0
next prev parent reply other threads:[~2019-04-01 10:45 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-01 10:45 [PATCH v3 0/7] arm64: Initial support for CVADP Andrew Murray
2019-04-01 10:45 ` Andrew Murray [this message]
2019-04-01 10:45 ` [PATCH v3 2/7] arm64: HWCAP: add support for AT_HWCAP2 Andrew Murray
2019-04-02 14:58 ` Dave Martin
2019-04-03 8:32 ` Andrew Murray
2019-04-03 9:11 ` Dave Martin
2019-04-03 9:29 ` Andrew Murray
2019-04-03 9:35 ` Dave Martin
2019-04-01 10:45 ` [PATCH v3 3/7] arm64: HWCAP: encapsulate elf_hwcap Andrew Murray
2019-04-02 14:58 ` Dave Martin
2019-04-02 15:06 ` Andrew Murray
2019-04-02 15:32 ` Suzuki K Poulose
2019-04-02 15:55 ` Dave Martin
2019-04-03 8:53 ` Andrew Murray
2019-04-03 9:13 ` Dave Martin
2019-04-01 10:45 ` [PATCH v3 4/7] arm64: Expose DC CVADP to userspace Andrew Murray
2019-04-01 10:45 ` [PATCH v3 5/7] arm64: add CVADP support to the cache maintenance helper Andrew Murray
2019-04-01 10:45 ` [PATCH v3 6/7] arm64: Advertise ARM64_HAS_DCPODP cpu feature Andrew Murray
2019-04-02 14:59 ` Dave Martin
2019-04-03 9:23 ` Andrew Murray
2019-04-03 9:32 ` Dave Martin
2019-04-03 9:57 ` Andrew Murray
2019-04-01 10:45 ` [PATCH v3 7/7] arm64: docs: document AT_HWCAP2 and unused AT_HWCAP bits Andrew Murray
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