From: Moritz Fischer <mdf@kernel.org>
To: Wu Hao <hao.wu@intel.com>
Cc: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
Luwei Kang <luwei.kang@intel.com>,
Russ Weight <russell.h.weight@intel.com>,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH 14/17] fpga: dfl: fme: add thermal management support
Date: Tue, 2 Apr 2019 07:59:25 -0700 [thread overview]
Message-ID: <20190402145925.GA15773@archbook> (raw)
In-Reply-To: <1553483264-5379-15-git-send-email-hao.wu@intel.com>
Hi Wu,
On Mon, Mar 25, 2019 at 11:07:41AM +0800, Wu Hao wrote:
> This patch adds support to thermal management private feature for DFL
> FPGA Management Engine (FME). As thermal throttling is handled by
> hardware automatically per pre-defined thresholds, this private
> feature driver only provides read-only sysfs interfaces for user
> to read temperature, thresholds, threshold policy and other info.
>
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> ---
> Documentation/ABI/testing/sysfs-platform-dfl-fme | 56 +++++++
> drivers/fpga/dfl-fme-main.c | 202 +++++++++++++++++++++++
> 2 files changed, 258 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme
> index b8327e9..d3aeb88 100644
> --- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
> +++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
> @@ -44,3 +44,59 @@ Description: Read-only. It returns socket_id to indicate which socket
> this FPGA belongs to, only valid for integrated solution.
> User only needs this information, in case standard numa node
> can't provide correct information.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/temperature
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns temperature (in Celsius) of this FPGA
> + device.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. Read this file to get the temperature threshold1
> + (in Celsius).
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold2
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. Read this file to get the temperature threshold2
> + (in Celsius).
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/trip_threshold
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns trip threshold (in Celsius), once FPGA
> + temperature reaches trip threshold, it triggers a fatal event
> + to board management controller (BMC) to shutdown FPGA.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1_status
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns 1 if temperature reaches threshold1,
> + otherwise 0. Once temperature reaches threshold1, hardware
> + will automatically enter throttling state (AP1 - 50%
> + or AP2 - 90% throttling, see 'threshold1_policy').
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold2_status
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns 1 if temperature reaches threshold2,
> + otherwise 0. Once temperature reaches threshold2, hardware
> + will automatically enter the deepest throttling state (AP6
> + - 100% throttling).
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1_policy
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. Read this file to get the policy of temperature
> + threshold1. It only supports two value (policy):
> + 0 - AP2 state (90% throttling)
> + 1 - AP1 state (50% throttling)
These look like they could directly map to the linux thermal framework,
any reason you can't use the thermal framework?
The trip stuff literally maps 1:1 to what a thermal driver does, I think
that's something you'd wanna consider.
Cheers,
Moritz
next prev parent reply other threads:[~2019-04-02 14:59 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 3:07 [PATCH 00/17] add new features for FPGA DFL drivers Wu Hao
2019-03-25 3:07 ` [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-03-25 17:28 ` Alan Tull
2019-04-01 19:54 ` Moritz Fischer
2019-04-02 4:38 ` Wu Hao
2019-04-02 13:33 ` Moritz Fischer
2019-03-25 3:07 ` [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-03-25 17:50 ` Alan Tull
2019-03-26 0:28 ` Wu Hao
2019-03-28 18:50 ` Alan Tull
2019-03-25 3:07 ` [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-03-25 18:48 ` Alan Tull
2019-03-25 22:53 ` Scott Wood
2019-03-25 22:58 ` Scott Wood
2019-03-26 19:33 ` Alan Tull
2019-03-26 21:22 ` Scott Wood
2019-03-27 4:37 ` Wu Hao
2019-03-27 6:10 ` Scott Wood
2019-03-27 6:03 ` Wu Hao
2019-03-27 5:10 ` Wu Hao
2019-03-27 6:19 ` Scott Wood
2019-03-27 7:10 ` Wu Hao
2019-03-27 5:46 ` Wu Hao
2019-03-25 3:07 ` [PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-03-25 3:07 ` [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 06/17] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-03-28 17:13 ` Alan Tull
2019-03-25 3:07 ` [PATCH 08/17] fpga: dfl: afu: add userclock " Wu Hao
2019-04-01 21:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-04-02 15:09 ` Moritz Fischer
2019-04-11 20:55 ` Alan Tull
2019-03-25 3:07 ` [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-04-02 15:50 ` Moritz Fischer
2019-04-11 20:45 ` Alan Tull
2019-03-25 3:07 ` [PATCH 11/17] fpga: dfl: afu: add error reporting support Wu Hao
2019-04-09 20:57 ` Alan Tull
2019-04-10 1:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-04-02 15:07 ` Moritz Fischer
2019-04-11 20:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-04-09 21:05 ` Alan Tull
2019-03-25 3:07 ` [PATCH 14/17] fpga: dfl: fme: add thermal management support Wu Hao
2019-04-02 14:59 ` Moritz Fischer [this message]
2019-04-03 16:31 ` Wu Hao
2019-04-03 18:09 ` Moritz Fischer
2019-04-03 23:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 15/17] fpga: dfl: fme: add power " Wu Hao
2019-04-11 20:07 ` Alan Tull
2019-04-12 2:50 ` Wu Hao
2019-04-15 21:17 ` Alan Tull
2019-04-17 7:36 ` Wu Hao
2019-04-12 21:05 ` Moritz Fischer
2019-04-17 7:31 ` Wu Hao
2019-03-25 3:07 ` [PATCH 16/17] fpga: dfl: fme: add global error reporting support Wu Hao
2019-04-09 21:35 ` Alan Tull
2019-04-10 1:34 ` Wu Hao
2019-03-25 3:07 ` [PATCH 17/17] fpga: dfl: fme: add performance " Wu Hao
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