From: Moritz Fischer <mdf@kernel.org>
To: Wu Hao <hao.wu@intel.com>
Cc: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver
Date: Tue, 2 Apr 2019 08:09:56 -0700 [thread overview]
Message-ID: <20190402150956.GC15773@archbook> (raw)
In-Reply-To: <1553483264-5379-10-git-send-email-hao.wu@intel.com>
Hi Wu,
On Mon, Mar 25, 2019 at 11:07:36AM +0800, Wu Hao wrote:
> This patch adds id_table for each dfl private feature driver,
> it allows to reuse same private feature driver to match and support
> multiple dfl private features.
>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> drivers/fpga/dfl-afu-main.c | 14 ++++++++++++--
> drivers/fpga/dfl-fme-main.c | 11 ++++++++---
> drivers/fpga/dfl-fme-pr.c | 7 ++++++-
> drivers/fpga/dfl-fme.h | 3 ++-
> drivers/fpga/dfl.c | 21 +++++++++++++++++++--
> drivers/fpga/dfl.h | 21 +++++++++++++++------
> 6 files changed, 62 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> index 82fd80a..2916876 100644
> --- a/drivers/fpga/dfl-afu-main.c
> +++ b/drivers/fpga/dfl-afu-main.c
> @@ -440,6 +440,11 @@ port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
> return ret;
> }
>
> +static const struct dfl_feature_id port_hdr_id_table[] = {
> + {.id = PORT_FEATURE_ID_HEADER,},
> + {0,}
> +};
> +
> static const struct dfl_feature_ops port_hdr_ops = {
> .init = port_hdr_init,
> .uinit = port_hdr_uinit,
> @@ -500,6 +505,11 @@ static void port_afu_uinit(struct platform_device *pdev,
> sysfs_remove_files(&pdev->dev.kobj, port_afu_attrs);
> }
>
> +static const struct dfl_feature_id port_afu_id_table[] = {
> + {.id = PORT_FEATURE_ID_AFU,},
> + {0,}
> +};
> +
> static const struct dfl_feature_ops port_afu_ops = {
> .init = port_afu_init,
> .uinit = port_afu_uinit,
> @@ -507,11 +517,11 @@ static const struct dfl_feature_ops port_afu_ops = {
>
> static struct dfl_feature_driver port_feature_drvs[] = {
> {
> - .id = PORT_FEATURE_ID_HEADER,
> + .id_table = port_hdr_id_table,
> .ops = &port_hdr_ops,
> },
> {
> - .id = PORT_FEATURE_ID_AFU,
> + .id_table = port_afu_id_table,
> .ops = &port_afu_ops,
> },
> {
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 8b2a337..38c6342 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -158,6 +158,11 @@ static long fme_hdr_ioctl(struct platform_device *pdev,
> return -ENODEV;
> }
>
> +static const struct dfl_feature_id fme_hdr_id_table[] = {
> + {.id = FME_FEATURE_ID_HEADER,},
> + {0,}
> +};
> +
> static const struct dfl_feature_ops fme_hdr_ops = {
> .init = fme_hdr_init,
> .uinit = fme_hdr_uinit,
> @@ -166,12 +171,12 @@ static const struct dfl_feature_ops fme_hdr_ops = {
>
> static struct dfl_feature_driver fme_feature_drvs[] = {
> {
> - .id = FME_FEATURE_ID_HEADER,
> + .id_table = fme_hdr_id_table,
> .ops = &fme_hdr_ops,
> },
> {
> - .id = FME_FEATURE_ID_PR_MGMT,
> - .ops = &pr_mgmt_ops,
> + .id_table = fme_pr_mgmt_id_table,
> + .ops = &fme_pr_mgmt_ops,
> },
> {
> .ops = NULL,
> diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
> index 8a0e46a..b054ac6 100644
> --- a/drivers/fpga/dfl-fme-pr.c
> +++ b/drivers/fpga/dfl-fme-pr.c
> @@ -482,7 +482,12 @@ static long fme_pr_ioctl(struct platform_device *pdev,
> return ret;
> }
>
> -const struct dfl_feature_ops pr_mgmt_ops = {
> +const struct dfl_feature_id fme_pr_mgmt_id_table[] = {
> + {.id = FME_FEATURE_ID_PR_MGMT,},
> + {0}
> +};
> +
> +const struct dfl_feature_ops fme_pr_mgmt_ops = {
> .init = pr_mgmt_init,
> .uinit = pr_mgmt_uinit,
> .ioctl = fme_pr_ioctl,
> diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h
> index de20755..7a021c4 100644
> --- a/drivers/fpga/dfl-fme.h
> +++ b/drivers/fpga/dfl-fme.h
> @@ -35,6 +35,7 @@ struct dfl_fme {
> struct dfl_feature_platform_data *pdata;
> };
>
> -extern const struct dfl_feature_ops pr_mgmt_ops;
> +extern const struct dfl_feature_ops fme_pr_mgmt_ops;
> +extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
>
> #endif /* __DFL_FME_H */
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index c5aa287..65f91ef 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -14,6 +14,8 @@
>
> #include "dfl.h"
>
> +#define DRV_VERSION "0.8"
> +
> static DEFINE_MUTEX(dfl_id_mutex);
>
> /*
> @@ -274,6 +276,21 @@ static int dfl_feature_instance_init(struct platform_device *pdev,
> return ret;
> }
>
> +static bool dfl_feature_drv_match(struct dfl_feature *feature,
> + struct dfl_feature_driver *driver)
> +{
> + const struct dfl_feature_id *ids = driver->id_table;
> +
> + if (ids) {
> + while (ids->id) {
> + if (ids->id == feature->id)
> + return true;
> + ids++;
> + }
> + }
> + return false;
> +}
> +
> /**
> * dfl_fpga_dev_feature_init - init for sub features of dfl feature device
> * @pdev: feature device.
> @@ -294,8 +311,7 @@ int dfl_fpga_dev_feature_init(struct platform_device *pdev,
>
> while (drv->ops) {
> dfl_fpga_dev_for_each_feature(pdata, feature) {
> - /* match feature and drv using id */
> - if (feature->id == drv->id) {
> + if (dfl_feature_drv_match(feature, drv)) {
> ret = dfl_feature_instance_init(pdev, pdata,
> feature, drv);
> if (ret)
> @@ -1164,3 +1180,4 @@ module_exit(dfl_fpga_exit);
> MODULE_DESCRIPTION("FPGA Device Feature List (DFL) Support");
> MODULE_AUTHOR("Intel Corporation");
> MODULE_LICENSE("GPL v2");
> +MODULE_VERSION(DRV_VERSION);
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 3c5dc3a..fbc57f0 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -30,8 +30,8 @@
> /* plus one for fme device */
> #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
>
> -/* Reserved 0x0 for Header Group Register and 0xff for AFU */
> -#define FEATURE_ID_FIU_HEADER 0x0
> +/* Reserved 0xfe for Header Group Register and 0xff for AFU */
> +#define FEATURE_ID_FIU_HEADER 0xfe
> #define FEATURE_ID_AFU 0xff
>
> #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
> @@ -169,13 +169,22 @@ void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
> int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
>
> /**
> - * struct dfl_feature_driver - sub feature's driver
> + * struct dfl_feature_id - dfl private feature id
> *
> - * @id: sub feature id.
> - * @ops: ops of this sub feature.
> + * @id: unique dfl private feature id.
> */
> -struct dfl_feature_driver {
> +struct dfl_feature_id {
> u64 id;
> +};
> +
> +/**
> + * struct dfl_feature_driver - dfl private feature driver
> + *
> + * @id_table: id_table for dfl private features supported by this driver.
> + * @ops: ops of this dfl private feature driver.
> + */
> +struct dfl_feature_driver {
> + const struct dfl_feature_id *id_table;
> const struct dfl_feature_ops *ops;
> };
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2019-04-02 15:09 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 3:07 [PATCH 00/17] add new features for FPGA DFL drivers Wu Hao
2019-03-25 3:07 ` [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-03-25 17:28 ` Alan Tull
2019-04-01 19:54 ` Moritz Fischer
2019-04-02 4:38 ` Wu Hao
2019-04-02 13:33 ` Moritz Fischer
2019-03-25 3:07 ` [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-03-25 17:50 ` Alan Tull
2019-03-26 0:28 ` Wu Hao
2019-03-28 18:50 ` Alan Tull
2019-03-25 3:07 ` [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-03-25 18:48 ` Alan Tull
2019-03-25 22:53 ` Scott Wood
2019-03-25 22:58 ` Scott Wood
2019-03-26 19:33 ` Alan Tull
2019-03-26 21:22 ` Scott Wood
2019-03-27 4:37 ` Wu Hao
2019-03-27 6:10 ` Scott Wood
2019-03-27 6:03 ` Wu Hao
2019-03-27 5:10 ` Wu Hao
2019-03-27 6:19 ` Scott Wood
2019-03-27 7:10 ` Wu Hao
2019-03-27 5:46 ` Wu Hao
2019-03-25 3:07 ` [PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-03-25 3:07 ` [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 06/17] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-03-28 17:13 ` Alan Tull
2019-03-25 3:07 ` [PATCH 08/17] fpga: dfl: afu: add userclock " Wu Hao
2019-04-01 21:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-04-02 15:09 ` Moritz Fischer [this message]
2019-04-11 20:55 ` Alan Tull
2019-03-25 3:07 ` [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-04-02 15:50 ` Moritz Fischer
2019-04-11 20:45 ` Alan Tull
2019-03-25 3:07 ` [PATCH 11/17] fpga: dfl: afu: add error reporting support Wu Hao
2019-04-09 20:57 ` Alan Tull
2019-04-10 1:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-04-02 15:07 ` Moritz Fischer
2019-04-11 20:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-04-09 21:05 ` Alan Tull
2019-03-25 3:07 ` [PATCH 14/17] fpga: dfl: fme: add thermal management support Wu Hao
2019-04-02 14:59 ` Moritz Fischer
2019-04-03 16:31 ` Wu Hao
2019-04-03 18:09 ` Moritz Fischer
2019-04-03 23:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 15/17] fpga: dfl: fme: add power " Wu Hao
2019-04-11 20:07 ` Alan Tull
2019-04-12 2:50 ` Wu Hao
2019-04-15 21:17 ` Alan Tull
2019-04-17 7:36 ` Wu Hao
2019-04-12 21:05 ` Moritz Fischer
2019-04-17 7:31 ` Wu Hao
2019-03-25 3:07 ` [PATCH 16/17] fpga: dfl: fme: add global error reporting support Wu Hao
2019-04-09 21:35 ` Alan Tull
2019-04-10 1:34 ` Wu Hao
2019-03-25 3:07 ` [PATCH 17/17] fpga: dfl: fme: add performance " Wu Hao
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