From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31A7BC4363D for ; Wed, 23 Sep 2020 21:29:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C28DF221EF for ; Wed, 23 Sep 2020 21:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726381AbgIWV31 (ORCPT ); Wed, 23 Sep 2020 17:29:27 -0400 Received: from mga11.intel.com ([192.55.52.93]:57381 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726265AbgIWV31 (ORCPT ); Wed, 23 Sep 2020 17:29:27 -0400 IronPort-SDR: zpmA06NSuWrFEJULGCjs7v0U4tY3fZfH7sQsQQ+s5mlrUWvSLqOl+0y/ZKYeAORmytpmISww3w 5fJ36uuRdcHQ== X-IronPort-AV: E=McAfee;i="6000,8403,9753"; a="158375537" X-IronPort-AV: E=Sophos;i="5.77,295,1596524400"; d="scan'208";a="158375537" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 14:29:27 -0700 IronPort-SDR: oG/dfcX9c8XEBHsFy+RgMu7uZo6ZO+S0IAC+V6fq3JjdHtLd9yuY9OIQq98sXgJkkBW5Ee18W0 mA5hSNUsfgUg== X-IronPort-AV: E=Sophos;i="5.77,295,1596524400"; d="scan'208";a="511797445" Received: from sjchrist-coffee.jf.intel.com (HELO linux.intel.com) ([10.54.74.160]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 14:29:26 -0700 Date: Wed, 23 Sep 2020 14:29:25 -0700 From: Sean Christopherson To: Andy Lutomirski Cc: Yu-cheng Yu , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , LKML , "open list:DOCUMENTATION" , Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang Subject: Re: [PATCH v12 8/8] x86: Disallow vsyscall emulation when CET is enabled Message-ID: <20200923212925.GC15101@linux.intel.com> References: <20200918192312.25978-1-yu-cheng.yu@intel.com> <20200918192312.25978-9-yu-cheng.yu@intel.com> <24718de58ab7bc6d7288c58d3567ad802eeb6542.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-api@vger.kernel.org On Mon, Sep 21, 2020 at 04:48:25PM -0700, Andy Lutomirski wrote: > On Mon, Sep 21, 2020 at 3:37 PM Yu-cheng Yu wrote: > > diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c > > b/arch/x86/entry/vsyscall/vsyscall_64.c > > index 44c33103a955..0131c9f7f9c5 100644 > > --- a/arch/x86/entry/vsyscall/vsyscall_64.c > > +++ b/arch/x86/entry/vsyscall/vsyscall_64.c > > @@ -38,6 +38,9 @@ > > #include > > #include > > #include > > +#include > > +#include > > +#include > > > > #define CREATE_TRACE_POINTS > > #include "vsyscall_trace.h" > > @@ -286,6 +289,32 @@ bool emulate_vsyscall(unsigned long error_code, > > /* Emulate a ret instruction. */ > > regs->ip = caller; > > regs->sp += 8; > > + > > + if (current->thread.cet.shstk_size || > > + current->thread.cet.ibt_enabled) { > > + u64 r; > > + > > + fpregs_lock(); > > + if (test_thread_flag(TIF_NEED_FPU_LOAD)) > > + __fpregs_load_activate(); > > Wouldn't this be nicer if you operated on the memory image, not the registers? > > > + > > +#ifdef CONFIG_X86_INTEL_BRANCH_TRACKING_USER > > + /* Fixup branch tracking */ > > + if (current->thread.cet.ibt_enabled) { > > + rdmsrl(MSR_IA32_U_CET, r); > > + wrmsrl(MSR_IA32_U_CET, r & ~CET_WAIT_ENDBR); > > + } > > +#endif > > Seems reasonable on first glance. > > > + > > +#ifdef CONFIG_X86_INTEL_SHADOW_STACK_USER > > + /* Unwind shadow stack. */ > > + if (current->thread.cet.shstk_size) { > > + rdmsrl(MSR_IA32_PL3_SSP, r); > > + wrmsrl(MSR_IA32_PL3_SSP, r + 8); > > + } > > +#endif > > What happens if the result is noncanonical? A quick skim of the SDM > didn't find anything. This latter issue goes away if you operate on > the memory image, though -- writing a bogus value is just fine, since > the FP restore will handle it. #GP, the SSP MSRs do canonical checks.