From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2206BC2B9F4 for ; Sat, 19 Jun 2021 15:16:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00BBF61264 for ; Sat, 19 Jun 2021 15:16:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234540AbhFSPSi (ORCPT ); Sat, 19 Jun 2021 11:18:38 -0400 Received: from gate.crashing.org ([63.228.1.57]:59443 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234128AbhFSPSh (ORCPT ); Sat, 19 Jun 2021 11:18:37 -0400 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 15JF26n5018966; Sat, 19 Jun 2021 10:02:07 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 15JF2288018951; Sat, 19 Jun 2021 10:02:02 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Sat, 19 Jun 2021 10:02:02 -0500 From: Segher Boessenkool To: Christophe Leroy Cc: Mathieu Desnoyers , maged michael , Peter Zijlstra , Dave Watson , Will Deacon , Andrew Hunter , David Sehr , Paul Mackerras , "H. Peter Anvin" , linux-arch , x86 , "Russell King, ARM Linux" , Greg Hackmann , Linus Torvalds , Ingo Molnar , Alan Stern , Paul , Andrea Parri , Avi Kivity , Boqun Feng , Nicholas Piggin , Alexander Viro , Andy Lutomirski , Thomas Gleixner , linux-api , linux-kernel , linuxppc-dev Subject: Re: [PATCH for 4.16 v7 02/11] powerpc: membarrier: Skip memory barrier in switch_mm() Message-ID: <20210619150202.GZ5077@gate.crashing.org> References: <20180129202020.8515-1-mathieu.desnoyers@efficios.com> <20180129202020.8515-3-mathieu.desnoyers@efficios.com> <8b200dd5-f37b-b208-82fb-2775df7bcd49@csgroup.eu> <2077369633.12794.1624037192994.JavaMail.zimbra@efficios.com> <4d2026cc-28e1-7781-fc95-e6160bd8db86@csgroup.eu> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4d2026cc-28e1-7781-fc95-e6160bd8db86@csgroup.eu> User-Agent: Mutt/1.4.2.3i Precedence: bulk List-ID: X-Mailing-List: linux-api@vger.kernel.org On Sat, Jun 19, 2021 at 11:35:34AM +0200, Christophe Leroy wrote: > > > Le 18/06/2021 à 19:26, Mathieu Desnoyers a écrit : > >----- On Jun 18, 2021, at 1:13 PM, Christophe Leroy > >christophe.leroy@csgroup.eu wrote: > >[...] > >> > >>I don't understand all that complexity to just replace a simple > >>'smp_mb__after_unlock_lock()'. > >> > >>#define smp_mb__after_unlock_lock() smp_mb() > >>#define smp_mb() barrier() > >># define barrier() __asm__ __volatile__("": : :"memory") > >> > >> > >>Am I missing some subtility ? > > > >On powerpc CONFIG_SMP, smp_mb() is actually defined as: > > > >#define smp_mb() __smp_mb() > >#define __smp_mb() mb() > >#define mb() __asm__ __volatile__ ("sync" : : : "memory") > > > >So the original motivation here was to skip a "sync" instruction whenever > >switching between threads which are part of the same process. But based on > >recent discussions, I suspect my implementation may be inaccurately doing > >so though. > > > > I see. > > Then, if you think a 'sync' is a concern, shouldn't we try and remove the > forest of 'sync' in the I/O accessors ? > > I can't really understand why we need all those 'sync' and 'isync' and > 'twi' around the accesses whereas I/O memory is usually mapped as 'Guarded' > so memory access ordering is already garantied. > > I'm sure we'll save a lot with that. The point of the twi in the I/O accessors was to make things easier to debug if the accesses fail: for the twi insn to complete the load will have to have completed as well. On a correctly working system you never should need this (until something fails ;-) ) Without the twi you might need to enforce ordering in some cases still. The twi is a very heavy hammer, but some of that that gives us is no doubt actually needed. Segher