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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id y23-20020a17090264d700b00176e2fa216csm7562816pli.52.2022.10.03.10.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 10:31:46 -0700 (PDT) Date: Mon, 3 Oct 2022 10:31:45 -0700 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Weijiang Yang , "Kirill A . Shutemov" , joao.moreira@intel.com, John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, Yu-cheng Yu Subject: Re: [PATCH v2 04/39] x86/cpufeatures: Enable CET CR4 bit for shadow stack Message-ID: <202210031031.E2942B66@keescook> References: <20220929222936.14584-1-rick.p.edgecombe@intel.com> <20220929222936.14584-5-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220929222936.14584-5-rick.p.edgecombe@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-api@vger.kernel.org On Thu, Sep 29, 2022 at 03:29:01PM -0700, Rick Edgecombe wrote: > From: Yu-cheng Yu > > Utilizing CET features requires a CR4 bit to be enabled as well as bits > to be set in CET MSRs. Setting the CR4 bit does two things: > 1. Enables the usage of WRUSS instruction, which the kernel can use to > write to userspace shadow stacks. > 2. Allows those individual aspects of CET to be enabled later via the MSR. > 3. Allows CET to be enabled in guests > > While future patches will allow the MSR values to be saved and restored > per task, the CR4 bit will allow for WRUSS to be used regardless of if a > tasks CET MSRs have been restored. > > Kernel IBT already enables the CET CR4 bit when it detects IBT HW support > and is configured with kernel IBT. However future patches that enable > userspace shadow stack support will need the bit set as well. So change > the logic to enable it in either case. > > Clear MSR_IA32_U_CET in cet_disable() so that it can't live to see > userspace in a new kexec-ed kernel that has CR4.CET set from kernel IBT. > > Signed-off-by: Yu-cheng Yu > Co-developed-by: Rick Edgecombe > Signed-off-by: Rick Edgecombe > Cc: Kees Cook Reviewed-by: Kees Cook -- Kees Cook