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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id 127-20020a621585000000b0056179d750efsm2665145pfv.103.2022.10.03.21.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 21:05:05 -0700 (PDT) Date: Mon, 3 Oct 2022 21:05:04 -0700 From: Kees Cook To: "Edgecombe, Rick P" Cc: "bsingharora@gmail.com" , "hpa@zytor.com" , "Syromiatnikov, Eugene" , "peterz@infradead.org" , "rdunlap@infradead.org" , "dave.hansen@linux.intel.com" , "kirill.shutemov@linux.intel.com" , "Eranian, Stephane" , "linux-mm@kvack.org" , "fweimer@redhat.com" , "nadav.amit@gmail.com" , "jannh@google.com" , "dethoma@microsoft.com" , "linux-arch@vger.kernel.org" , "kcc@google.com" , "bp@alien8.de" , "oleg@redhat.com" , "hjl.tools@gmail.com" , "Yang, Weijiang" , "Lutomirski, Andy" , "pavel@ucw.cz" , "arnd@arndb.de" , "Moreira, Joao" , "tglx@linutronix.de" , "mike.kravetz@oracle.com" , "x86@kernel.org" , "linux-doc@vger.kernel.org" , "jamorris@linux.microsoft.com" , "john.allen@amd.com" , "rppt@kernel.org" , "mingo@redhat.com" , "Shankar, Ravi V" , "corbet@lwn.net" , "linux-kernel@vger.kernel.org" , "linux-api@vger.kernel.org" , "gorcunov@gmail.com" Subject: Re: [PATCH v2 06/39] x86/fpu: Add helper for modifying xstate Message-ID: <202210032104.A1029D23@keescook> References: <20220929222936.14584-1-rick.p.edgecombe@intel.com> <20220929222936.14584-7-rick.p.edgecombe@intel.com> <202210031045.419F7DB396@keescook> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-api@vger.kernel.org On Mon, Oct 03, 2022 at 08:05:13PM +0000, Edgecombe, Rick P wrote: > On Mon, 2022-10-03 at 10:48 -0700, Kees Cook wrote: > > > The easiest way to modify supervisor xfeature data is to force > > > restore > > > the registers and write directly to the MSRs. Often times this is > > > just fine > > > anyway as the registers need to be restored before returning to > > > userspace. > > > Do this for now, leaving buffer writing optimizations for the > > > future. > > > > Just for my own clarity, does this mean lock/load _needs_ to happen > > before MSR access, or is it just a convenient place to do it? From > > later > > patches it seems it's a requirement during MSR access, which might be > > a > > good idea to detail here. It answers the question "when is this > > function > > needed?" > > The CET state is xsaves managed. It gets lazily restored before > returning to userspace with the rest of the fpu stuff. This function > will force restore all the fpu state to the registers early and lock > them from being automatically saved/restored. Then the tasks CET state > can be modified in the MSRs, before unlocking the fpregs. Last time I > tried to modify the state directly in the xsave buffer when it was > efficient, but it had issues and Thomas suggested this. Okay, gotcha. Thanks! -- Kees Cook